SPI_DEVICE/2P Simulation Results

Friday July 26 2024 23:02:17 UTC

GitHub Revision: 4877b481e8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 32772136499307530671572864311472020383177374948143841887013058662761887638244

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	11.018m	344.841ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.410s	91.764us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.690s	501.590us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	26.090s	6.469ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	24.100s	1.150ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.970s	120.244us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.690s	501.590us	20	20	100.00
		spi_device_csr_aliasing	24.100s	1.150ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.720s	12.862us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.770s	235.050us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.840s	18.877us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.100s	85.809us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.790s	16.892us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	6.390s	166.147us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	6.390s	166.147us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	24.230s	9.075ms	50	50	100.00
		spi_device_tpm_sts_read	1.000s	206.543us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	50.530s	20.099ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	46.420s	68.274ms	50	50	100.00
		spi_device_flash_all	6.866m	122.717ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	35.610s	38.223ms	50	50	100.00
		spi_device_flash_all	6.866m	122.717ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	35.610s	38.223ms	50	50	100.00
		spi_device_flash_all	6.866m	122.717ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	6.866m	122.717ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	39.410s	9.676ms	50	50	100.00
		spi_device_flash_all	6.866m	122.717ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	39.410s	9.676ms	50	50	100.00
		spi_device_flash_all	6.866m	122.717ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	39.410s	9.676ms	50	50	100.00
		spi_device_flash_all	6.866m	122.717ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	39.410s	9.676ms	50	50	100.00
		spi_device_flash_all	6.866m	122.717ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	39.410s	9.676ms	50	50	100.00
		spi_device_flash_all	6.866m	122.717ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	33.180s	27.435ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.957m	183.916ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.957m	183.916ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.957m	183.916ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.145m	4.494ms	50	50	100.00
		spi_device_read_buffer_direct	19.050s	3.171ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.957m	183.916ms	50	50	100.00
		spi_device_flash_all	6.866m	122.717ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	6.866m	122.717ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	6.866m	122.717ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	19.910s	6.225ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	19.910s	6.225ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	11.018m	344.841ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	8.594m	67.016ms	50	50	100.00
V2	stress_all	spi_device_stress_all	17.306m	324.131ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.810s	15.993us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.790s	21.092us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.340s	240.907us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.340s	240.907us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.410s	91.764us	5	5	100.00
		spi_device_csr_rw	2.690s	501.590us	20	20	100.00
		spi_device_csr_aliasing	24.100s	1.150ms	5	5	100.00
		spi_device_same_csr_outstanding	3.980s	390.413us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.410s	91.764us	5	5	100.00
		spi_device_csr_rw	2.690s	501.590us	20	20	100.00
		spi_device_csr_aliasing	24.100s	1.150ms	5	5	100.00
		spi_device_same_csr_outstanding	3.980s	390.413us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.260s	582.913us	5	5	100.00
		spi_device_tl_intg_err	19.860s	1.461ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	19.860s	1.461ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	7.600m	65.392ms	50	50	100.00
		TOTAL			1151	1151	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	98.44	94.08	98.62	89.36	97.28	95.43	99.26

Past Results

• Latest
• 2024.07.26_09.13.39
• 2024.07.25_08.45.19
• 2024.07.24_08.25.21
• 2024.07.23_08.57.28
• 2024.07.22_08.56.43
• 2024.07.21_08.37.39
• 2024.07.20_10.01.54