SPI_DEVICE/2P Simulation Results

Saturday July 27 2024 23:02:25 UTC

GitHub Revision: eca25c0ff8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 6528518538521148567139195500524222710943459299328477504124649113671643189924

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	9.196m	280.949ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.190s	127.227us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.720s	114.712us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	27.080s	1.881ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	21.320s	1.197ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.920s	158.054us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.720s	114.712us	20	20	100.00
		spi_device_csr_aliasing	21.320s	1.197ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.700s	11.368us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.750s	200.805us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.840s	61.690us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.100s	183.876us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.710s	28.410us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	10.870s	1.405ms	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	10.870s	1.405ms	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	26.670s	9.310ms	50	50	100.00
		spi_device_tpm_sts_read	1.030s	781.755us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	43.560s	32.595ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	40.090s	31.503ms	50	50	100.00
		spi_device_flash_all	8.093m	70.314ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	29.270s	48.698ms	50	50	100.00
		spi_device_flash_all	8.093m	70.314ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	29.270s	48.698ms	50	50	100.00
		spi_device_flash_all	8.093m	70.314ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	8.093m	70.314ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	43.710s	6.503ms	50	50	100.00
		spi_device_flash_all	8.093m	70.314ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	43.710s	6.503ms	50	50	100.00
		spi_device_flash_all	8.093m	70.314ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	43.710s	6.503ms	50	50	100.00
		spi_device_flash_all	8.093m	70.314ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	43.710s	6.503ms	50	50	100.00
		spi_device_flash_all	8.093m	70.314ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	43.710s	6.503ms	50	50	100.00
		spi_device_flash_all	8.093m	70.314ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	31.310s	46.684ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.657m	12.892ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.657m	12.892ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.657m	12.892ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.132m	19.252ms	50	50	100.00
		spi_device_read_buffer_direct	25.770s	2.382ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.657m	12.892ms	50	50	100.00
		spi_device_flash_all	8.093m	70.314ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	8.093m	70.314ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	8.093m	70.314ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	15.850s	3.392ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	15.850s	3.392ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	9.196m	280.949ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	7.552m	51.206ms	50	50	100.00
V2	stress_all	spi_device_stress_all	16.263m	516.618ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.790s	26.555us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.810s	150.055us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.900s	878.945us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.900s	878.945us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.190s	127.227us	5	5	100.00
		spi_device_csr_rw	2.720s	114.712us	20	20	100.00
		spi_device_csr_aliasing	21.320s	1.197ms	5	5	100.00
		spi_device_same_csr_outstanding	3.850s	156.397us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.190s	127.227us	5	5	100.00
		spi_device_csr_rw	2.720s	114.712us	20	20	100.00
		spi_device_csr_aliasing	21.320s	1.197ms	5	5	100.00
		spi_device_same_csr_outstanding	3.850s	156.397us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.190s	87.532us	5	5	100.00
		spi_device_tl_intg_err	23.500s	857.524us	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	23.500s	857.524us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	30.414m	1.500s	48	50	96.00
		TOTAL			1149	1151	99.83

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.06	98.44	94.10	98.62	89.36	97.28	95.43	99.21

Failure Buckets

• Job spi_device_2p-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:

  • Test spi_device_flash_mode_ignore_cmds has 1 failures.

    • 22.spi_device_flash_mode_ignore_cmds.105242984061526262898376068034586290077564639357765232296997958869439366746618
      Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/22.spi_device_flash_mode_ignore_cmds/latest/run.log

        Job ID: smart:9548b5e8-348a-4ad9-97ee-d745c335af34
      

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test spi_device_flash_mode_ignore_cmds has 1 failures.

    • 41.spi_device_flash_mode_ignore_cmds.9988740179862506258157569365482127057967604997108441720369419397234744710866
      Line 262, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/41.spi_device_flash_mode_ignore_cmds/latest/run.log

        UVM_FATAL @ 1500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1500000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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