SPI_DEVICE/2P Simulation Results

Sunday July 28 2024 23:02:28 UTC

GitHub Revision: eca25c0ff8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 35694793988142953409419697382868702825984401131209466119932029294128690866559

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	12.969m	338.516ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.410s	57.343us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.850s	782.675us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	34.410s	9.811ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	15.120s	2.522ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.260s	113.298us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.850s	782.675us	20	20	100.00
		spi_device_csr_aliasing	15.120s	2.522ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.710s	38.122us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.170s	260.815us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.840s	28.507us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.160s	59.048us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.740s	22.128us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	8.630s	661.571us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	8.630s	661.571us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	26.270s	10.670ms	50	50	100.00
		spi_device_tpm_sts_read	1.080s	100.800us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	44.480s	7.652ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	26.230s	8.213ms	50	50	100.00
		spi_device_flash_all	9.609m	83.748ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	31.300s	11.449ms	50	50	100.00
		spi_device_flash_all	9.609m	83.748ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	31.300s	11.449ms	50	50	100.00
		spi_device_flash_all	9.609m	83.748ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	9.609m	83.748ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	30.180s	6.455ms	50	50	100.00
		spi_device_flash_all	9.609m	83.748ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	30.180s	6.455ms	50	50	100.00
		spi_device_flash_all	9.609m	83.748ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	30.180s	6.455ms	50	50	100.00
		spi_device_flash_all	9.609m	83.748ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	30.180s	6.455ms	50	50	100.00
		spi_device_flash_all	9.609m	83.748ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	30.180s	6.455ms	50	50	100.00
		spi_device_flash_all	9.609m	83.748ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	51.760s	83.852ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	3.150m	65.892ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	3.150m	65.892ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	3.150m	65.892ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	59.270s	6.041ms	50	50	100.00
		spi_device_read_buffer_direct	22.800s	1.989ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	3.150m	65.892ms	50	50	100.00
		spi_device_flash_all	9.609m	83.748ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	9.609m	83.748ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	9.609m	83.748ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	18.060s	1.904ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	18.060s	1.904ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	12.969m	338.516ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	11.979m	336.616ms	50	50	100.00
V2	stress_all	spi_device_stress_all	14.181m	367.136ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.810s	16.145us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.800s	14.607us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.730s	676.546us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.730s	676.546us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.410s	57.343us	5	5	100.00
		spi_device_csr_rw	2.850s	782.675us	20	20	100.00
		spi_device_csr_aliasing	15.120s	2.522ms	5	5	100.00
		spi_device_same_csr_outstanding	4.190s	255.970us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.410s	57.343us	5	5	100.00
		spi_device_csr_rw	2.850s	782.675us	20	20	100.00
		spi_device_csr_aliasing	15.120s	2.522ms	5	5	100.00
		spi_device_same_csr_outstanding	4.190s	255.970us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.220s	325.012us	5	5	100.00
		spi_device_tl_intg_err	23.590s	2.148ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	23.590s	2.148ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	9.124m	161.788ms	49	50	98.00
		TOTAL			1150	1151	99.91

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	98.44	94.08	98.62	89.36	97.28	95.43	99.26

Failure Buckets

• UVM_ERROR (spi_device_pass_base_vseq.sv:704) [spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be * has 1 failures:
  • Test spi_device_flash_mode_ignore_cmds has 1 failures.

    • 42.spi_device_flash_mode_ignore_cmds.86630479730759288623659049560800500829151811146597620525302769478939943411438
      Line 277, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/42.spi_device_flash_mode_ignore_cmds/latest/run.log

        UVM_ERROR @ 27662799336 ps: (spi_device_pass_base_vseq.sv:704) [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
        tl_ul_fuzzy_flash_status_q[i] = 0x69e0f4
        UVM_INFO @ 32651083956 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 8/9
        UVM_INFO @ 32678584676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.07.28_10.59.18
• 2024.07.27_09.51.36
• 2024.07.26_09.13.39
• 2024.07.25_08.45.19
• 2024.07.24_08.25.21
• 2024.07.23_08.57.28
• 2024.07.22_08.56.43