SPI_DEVICE/2P Simulation Results

Monday July 29 2024 23:02:32 UTC

GitHub Revision: `39f3866b56`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 91682663165753342493852681547271085771042321116470426223748766059309541455602

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	10.106m	389.218ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.350s	22.066us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.690s	43.095us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	42.690s	3.251ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	20.770s	2.494ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.000s	245.167us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.690s	43.095us	20	20	100.00
		spi_device_csr_aliasing	20.770s	2.494ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.670s	11.183us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.060s	46.464us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.830s	51.667us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.180s	80.771us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.750s	15.787us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	8.080s	128.117us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	8.080s	128.117us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	25.000s	40.505ms	50	50	100.00
		spi_device_tpm_sts_read	0.980s	87.174us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	40.690s	15.622ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	25.470s	15.494ms	50	50	100.00
		spi_device_flash_all	9.599m	323.137ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	28.910s	7.285ms	50	50	100.00
		spi_device_flash_all	9.599m	323.137ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	28.910s	7.285ms	50	50	100.00
		spi_device_flash_all	9.599m	323.137ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	9.599m	323.137ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	29.010s	2.974ms	50	50	100.00
		spi_device_flash_all	9.599m	323.137ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	29.010s	2.974ms	50	50	100.00
		spi_device_flash_all	9.599m	323.137ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	29.010s	2.974ms	50	50	100.00
		spi_device_flash_all	9.599m	323.137ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	29.010s	2.974ms	50	50	100.00
		spi_device_flash_all	9.599m	323.137ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	29.010s	2.974ms	50	50	100.00
		spi_device_flash_all	9.599m	323.137ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	21.550s	4.576ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.805m	18.284ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.805m	18.284ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.805m	18.284ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	51.480s	14.483ms	50	50	100.00
		spi_device_read_buffer_direct	21.750s	7.365ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.805m	18.284ms	50	50	100.00
		spi_device_flash_all	9.599m	323.137ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	9.599m	323.137ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	9.599m	323.137ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	24.230s	2.239ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	24.230s	2.239ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	10.106m	389.218ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	13.821m	177.836ms	50	50	100.00
V2	stress_all	spi_device_stress_all	9.424m	64.044ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.830s	20.782us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.800s	18.627us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.720s	198.764us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.720s	198.764us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.350s	22.066us	5	5	100.00
		spi_device_csr_rw	2.690s	43.095us	20	20	100.00
		spi_device_csr_aliasing	20.770s	2.494ms	5	5	100.00
		spi_device_same_csr_outstanding	4.120s	245.095us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.350s	22.066us	5	5	100.00
		spi_device_csr_rw	2.690s	43.095us	20	20	100.00
		spi_device_csr_aliasing	20.770s	2.494ms	5	5	100.00
		spi_device_same_csr_outstanding	4.120s	245.095us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.240s	372.003us	5	5	100.00
		spi_device_tl_intg_err	23.640s	1.098ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	23.640s	1.098ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	7.857m	142.112ms	49	50	98.00
		TOTAL			1150	1151	99.91

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.06	98.45	94.08	98.62	89.36	97.29	95.43	99.21

Failure Buckets

UVM_ERROR (spi_device_pass_base_vseq.sv:704) [spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be *

has 1 failures:

Test spi_device_flash_mode_ignore_cmds has 1 failures.

35.spi_device_flash_mode_ignore_cmds.101479683780365403893985319225523062235682133358250591598747242825457476021636
Line 259, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/35.spi_device_flash_mode_ignore_cmds/latest/run.log

  UVM_ERROR @ 44908523426 ps: (spi_device_pass_base_vseq.sv:704) [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  tl_ul_fuzzy_flash_status_q[i] = 0xb3a2d6
  tl_ul_fuzzy_flash_status_q[i] = 0xb3a2d6
  tl_ul_fuzzy_flash_status_q[i] = 0xb3a2d6
  UVM_INFO @ 63793208162 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 2/8