SPI_DEVICE/2P Simulation Results

Tuesday July 30 2024 23:02:08 UTC

GitHub Revision: fdfa12db04

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 101467584611478134588291649782725219255540557286164709436567235390830780957271

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	14.691m	445.087ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.420s	91.130us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.070s	131.646us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	31.820s	546.753us	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	23.470s	5.676ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.980s	266.185us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.070s	131.646us	20	20	100.00
		spi_device_csr_aliasing	23.470s	5.676ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.770s	12.319us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.140s	35.654us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.860s	72.909us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.240s	123.072us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.730s	38.393us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	12.190s	719.535us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	12.190s	719.535us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	27.300s	20.854ms	50	50	100.00
		spi_device_tpm_sts_read	1.010s	66.531us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	50.160s	10.834ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	38.460s	93.847ms	50	50	100.00
		spi_device_flash_all	6.223m	300.726ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	27.410s	21.392ms	50	50	100.00
		spi_device_flash_all	6.223m	300.726ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	27.410s	21.392ms	50	50	100.00
		spi_device_flash_all	6.223m	300.726ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	6.223m	300.726ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	34.410s	10.616ms	50	50	100.00
		spi_device_flash_all	6.223m	300.726ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	34.410s	10.616ms	50	50	100.00
		spi_device_flash_all	6.223m	300.726ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	34.410s	10.616ms	50	50	100.00
		spi_device_flash_all	6.223m	300.726ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	34.410s	10.616ms	50	50	100.00
		spi_device_flash_all	6.223m	300.726ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	34.410s	10.616ms	50	50	100.00
		spi_device_flash_all	6.223m	300.726ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	40.780s	37.389ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.488m	72.189ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.488m	72.189ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.488m	72.189ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	59.970s	24.964ms	50	50	100.00
		spi_device_read_buffer_direct	21.630s	6.344ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.488m	72.189ms	50	50	100.00
		spi_device_flash_all	6.223m	300.726ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	6.223m	300.726ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	6.223m	300.726ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	19.580s	2.341ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	19.580s	2.341ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	14.691m	445.087ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	12.478m	492.923ms	50	50	100.00
V2	stress_all	spi_device_stress_all	17.773m	116.523ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.800s	14.627us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.910s	54.016us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	6.560s	4.307ms	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	6.560s	4.307ms	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.420s	91.130us	5	5	100.00
		spi_device_csr_rw	3.070s	131.646us	20	20	100.00
		spi_device_csr_aliasing	23.470s	5.676ms	5	5	100.00
		spi_device_same_csr_outstanding	5.960s	170.689us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.420s	91.130us	5	5	100.00
		spi_device_csr_rw	3.070s	131.646us	20	20	100.00
		spi_device_csr_aliasing	23.470s	5.676ms	5	5	100.00
		spi_device_same_csr_outstanding	5.960s	170.689us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.190s	343.011us	5	5	100.00
		spi_device_tl_intg_err	27.670s	5.466ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	27.670s	5.466ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	9.086m	81.431ms	50	50	100.00
		TOTAL			1151	1151	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	98.44	94.08	98.62	89.36	97.28	95.43	99.26

Past Results

• Latest
• 2024.07.30_09.35.20
• 2024.07.29_08.00.25
• 2024.07.28_10.59.18
• 2024.07.27_09.51.36
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