SPI_DEVICE/2P Simulation Results

Wednesday July 31 2024 23:02:38 UTC

GitHub Revision: e9b7e615a7

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 25204348267605859133056659113100703417171299070132656462514712657132693373848

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	8.169m	59.672ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.430s	46.340us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.820s	120.186us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	25.550s	7.182ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	23.680s	1.150ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.870s	296.342us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.820s	120.186us	20	20	100.00
		spi_device_csr_aliasing	23.680s	1.150ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.700s	13.982us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.140s	61.553us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.880s	15.936us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.160s	101.691us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.750s	22.025us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	11.870s	295.644us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	11.870s	295.644us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	24.480s	34.387ms	50	50	100.00
		spi_device_tpm_sts_read	1.020s	272.526us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	40.420s	7.888ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	36.070s	44.923ms	50	50	100.00
		spi_device_flash_all	6.453m	49.882ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	25.410s	15.461ms	50	50	100.00
		spi_device_flash_all	6.453m	49.882ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	25.410s	15.461ms	50	50	100.00
		spi_device_flash_all	6.453m	49.882ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	6.453m	49.882ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	32.330s	3.730ms	50	50	100.00
		spi_device_flash_all	6.453m	49.882ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	32.330s	3.730ms	50	50	100.00
		spi_device_flash_all	6.453m	49.882ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	32.330s	3.730ms	50	50	100.00
		spi_device_flash_all	6.453m	49.882ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	32.330s	3.730ms	50	50	100.00
		spi_device_flash_all	6.453m	49.882ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	32.330s	3.730ms	50	50	100.00
		spi_device_flash_all	6.453m	49.882ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	29.570s	9.870ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	3.221m	333.560ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	3.221m	333.560ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	3.221m	333.560ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	57.120s	5.205ms	50	50	100.00
		spi_device_read_buffer_direct	23.970s	2.072ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	3.221m	333.560ms	50	50	100.00
		spi_device_flash_all	6.453m	49.882ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	6.453m	49.882ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	6.453m	49.882ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	33.080s	7.045ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	33.080s	7.045ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	8.169m	59.672ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	12.331m	91.674ms	50	50	100.00
V2	stress_all	spi_device_stress_all	16.448m	101.539ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.820s	15.609us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.800s	87.376us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.610s	496.470us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.610s	496.470us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.430s	46.340us	5	5	100.00
		spi_device_csr_rw	2.820s	120.186us	20	20	100.00
		spi_device_csr_aliasing	23.680s	1.150ms	5	5	100.00
		spi_device_same_csr_outstanding	4.300s	1.745ms	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.430s	46.340us	5	5	100.00
		spi_device_csr_rw	2.820s	120.186us	20	20	100.00
		spi_device_csr_aliasing	23.680s	1.150ms	5	5	100.00
		spi_device_same_csr_outstanding	4.300s	1.745ms	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.200s	158.799us	5	5	100.00
		spi_device_tl_intg_err	21.900s	3.034ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	21.900s	3.034ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	6.244m	320.358ms	50	50	100.00
		TOTAL			1151	1151	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	98.44	94.08	98.62	89.36	97.28	95.43	99.26

Past Results

• Latest
• 2024.07.31_09.16.35
• 2024.07.30_09.35.20
• 2024.07.29_08.00.25
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