SPI_DEVICE/2P Simulation Results

Thursday August 01 2024 23:02:20 UTC

GitHub Revision: `625f353e9c`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85273092133191575795496895645039765542965103003083525273509664765586668778052

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	9.154m	248.429ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.410s	142.392us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.060s	1.010ms	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	38.340s	5.204ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	22.930s	4.585ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.060s	636.978us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.060s	1.010ms	20	20	100.00
		spi_device_csr_aliasing	22.930s	4.585ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.670s	28.434us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.140s	125.965us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.910s	53.674us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.150s	27.317us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.770s	15.982us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	13.160s	1.301ms	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	13.160s	1.301ms	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	25.200s	8.161ms	50	50	100.00
		spi_device_tpm_sts_read	0.990s	507.071us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	42.870s	8.528ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	24.140s	18.626ms	50	50	100.00
		spi_device_flash_all	7.830m	66.803ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	27.320s	34.738ms	50	50	100.00
		spi_device_flash_all	7.830m	66.803ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	27.320s	34.738ms	50	50	100.00
		spi_device_flash_all	7.830m	66.803ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	7.830m	66.803ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	30.340s	6.306ms	50	50	100.00
		spi_device_flash_all	7.830m	66.803ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	30.340s	6.306ms	50	50	100.00
		spi_device_flash_all	7.830m	66.803ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	30.340s	6.306ms	50	50	100.00
		spi_device_flash_all	7.830m	66.803ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	30.340s	6.306ms	50	50	100.00
		spi_device_flash_all	7.830m	66.803ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	30.340s	6.306ms	50	50	100.00
		spi_device_flash_all	7.830m	66.803ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	30.760s	43.429ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.324m	13.809ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.324m	13.809ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.324m	13.809ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.591m	8.765ms	50	50	100.00
		spi_device_read_buffer_direct	24.290s	7.904ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.324m	13.809ms	50	50	100.00
		spi_device_flash_all	7.830m	66.803ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	7.830m	66.803ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	7.830m	66.803ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	35.440s	2.957ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	35.440s	2.957ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	9.154m	248.429ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	11.506m	140.545ms	50	50	100.00
V2	stress_all	spi_device_stress_all	16.146m	202.299ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.760s	14.235us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.790s	139.643us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	6.160s	440.934us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	6.160s	440.934us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.410s	142.392us	5	5	100.00
		spi_device_csr_rw	3.060s	1.010ms	20	20	100.00
		spi_device_csr_aliasing	22.930s	4.585ms	5	5	100.00
		spi_device_same_csr_outstanding	4.140s	158.294us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.410s	142.392us	5	5	100.00
		spi_device_csr_rw	3.060s	1.010ms	20	20	100.00
		spi_device_csr_aliasing	22.930s	4.585ms	5	5	100.00
		spi_device_same_csr_outstanding	4.140s	158.294us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.160s	1.036ms	5	5	100.00
		spi_device_tl_intg_err	24.890s	1.049ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	24.890s	1.049ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	49.965m	1.500s	48	50	96.00
		TOTAL			1149	1151	99.83

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.06	98.44	94.08	98.62	89.36	97.29	95.43	99.21

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test spi_device_flash_mode_ignore_cmds has 1 failures.
  - 19.spi_device_flash_mode_ignore_cmds.112229732759903111015159055871609231568899722898303784093804318333421862624022
    Line 259, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/19.spi_device_flash_mode_ignore_cmds/latest/run.log
```
  UVM_FATAL @ 1500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1500000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (spi_device_pass_base_vseq.sv:704) [spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be * has 1 failures:
- Test spi_device_flash_mode_ignore_cmds has 1 failures.
  - 30.spi_device_flash_mode_ignore_cmds.29241761463429713969344834804575983232677028356908940963504299430325826262015
    Line 278, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/30.spi_device_flash_mode_ignore_cmds/latest/run.log
```
  UVM_ERROR @ 29329471001 ps: (spi_device_pass_base_vseq.sv:704) [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  tl_ul_fuzzy_flash_status_q[i] = 0x90ba64
  tl_ul_fuzzy_flash_status_q[i] = 0x90ba64
  tl_ul_fuzzy_flash_status_q[i] = 0x4d36ec
  tl_ul_fuzzy_flash_status_q[i] = 0x664ee4
```

SPI_DEVICE/2P Simulation Results

Thursday August 01 2024 23:02:20 UTC

GitHub Revision: 625f353e9c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85273092133191575795496895645039765542965103003083525273509664765586668778052

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `625f353e9c`