SPI_DEVICE/2P Simulation Results

Friday August 02 2024 23:02:48 UTC

GitHub Revision: `c8985d6745`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 75989420798843487383163268541581889763599806834398027919895759109584083292465

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	9.823m	116.198ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.210s	38.091us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.790s	120.015us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	36.220s	8.994ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	23.790s	3.219ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.070s	169.232us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.790s	120.015us	20	20	100.00
		spi_device_csr_aliasing	23.790s	3.219ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.670s	10.800us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.100s	69.003us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.840s	38.062us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.110s	25.115us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.790s	16.717us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	11.140s	1.372ms	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	11.140s	1.372ms	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	22.710s	17.179ms	50	50	100.00
		spi_device_tpm_sts_read	1.120s	139.721us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	47.530s	19.173ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	25.860s	20.821ms	50	50	100.00
		spi_device_flash_all	6.745m	235.632ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	24.420s	17.834ms	50	50	100.00
		spi_device_flash_all	6.745m	235.632ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	24.420s	17.834ms	50	50	100.00
		spi_device_flash_all	6.745m	235.632ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	6.745m	235.632ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	31.070s	9.584ms	50	50	100.00
		spi_device_flash_all	6.745m	235.632ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	31.070s	9.584ms	50	50	100.00
		spi_device_flash_all	6.745m	235.632ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	31.070s	9.584ms	50	50	100.00
		spi_device_flash_all	6.745m	235.632ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	31.070s	9.584ms	50	50	100.00
		spi_device_flash_all	6.745m	235.632ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	31.070s	9.584ms	50	50	100.00
		spi_device_flash_all	6.745m	235.632ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	34.100s	36.557ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.660m	7.699ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.660m	7.699ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.660m	7.699ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.336m	6.563ms	50	50	100.00
		spi_device_read_buffer_direct	26.100s	4.652ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.660m	7.699ms	50	50	100.00
		spi_device_flash_all	6.745m	235.632ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	6.745m	235.632ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	6.745m	235.632ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	31.120s	11.968ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	31.120s	11.968ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	9.823m	116.198ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	9.954m	63.692ms	50	50	100.00
V2	stress_all	spi_device_stress_all	12.739m	88.276ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.790s	38.779us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.840s	17.055us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	6.320s	218.013us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	6.320s	218.013us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.210s	38.091us	5	5	100.00
		spi_device_csr_rw	2.790s	120.015us	20	20	100.00
		spi_device_csr_aliasing	23.790s	3.219ms	5	5	100.00
		spi_device_same_csr_outstanding	4.400s	157.139us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.210s	38.091us	5	5	100.00
		spi_device_csr_rw	2.790s	120.015us	20	20	100.00
		spi_device_csr_aliasing	23.790s	3.219ms	5	5	100.00
		spi_device_same_csr_outstanding	4.400s	157.139us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.170s	116.785us	5	5	100.00
		spi_device_tl_intg_err	21.380s	3.742ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	21.380s	3.742ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	6.418m	202.200ms	49	50	98.00
		TOTAL			1150	1151	99.91

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	98.44	94.08	98.62	89.36	97.28	95.43	99.26

Failure Buckets

UVM_ERROR (spi_device_pass_base_vseq.sv:704) [spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be *

has 1 failures:

Test spi_device_flash_mode_ignore_cmds has 1 failures.

31.spi_device_flash_mode_ignore_cmds.38372708673130982272763576433734155589857807438845947497468058227324435862957
Line 254, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/31.spi_device_flash_mode_ignore_cmds/latest/run.log

  UVM_ERROR @ 13957093044 ps: (spi_device_pass_base_vseq.sv:704) [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  tl_ul_fuzzy_flash_status_q[i] = 0xe0c4a0
  tl_ul_fuzzy_flash_status_q[i] = 0x8cc850
  UVM_INFO @ 16253660414 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 1/8
  UVM_INFO @ 16253660414 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 2/8