SPI_DEVICE/2P Simulation Results

Saturday August 03 2024 23:02:32 UTC

GitHub Revision: c8985d6745

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 108668412464624965510474525856307009670790505545344576298908689226672042444441

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	11.332m	267.696ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.300s	23.368us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.860s	181.937us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	30.180s	5.233ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	9.090s	424.913us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.990s	162.542us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.860s	181.937us	20	20	100.00
		spi_device_csr_aliasing	9.090s	424.913us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.730s	22.039us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.300s	139.586us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.840s	15.235us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.180s	35.469us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.730s	38.731us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	11.090s	247.333us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	11.090s	247.333us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	23.410s	10.170ms	50	50	100.00
		spi_device_tpm_sts_read	1.170s	685.477us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	54.430s	11.439ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	19.730s	29.080ms	50	50	100.00
		spi_device_flash_all	7.649m	130.783ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	31.200s	29.610ms	50	50	100.00
		spi_device_flash_all	7.649m	130.783ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	31.200s	29.610ms	50	50	100.00
		spi_device_flash_all	7.649m	130.783ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	7.649m	130.783ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	27.900s	5.978ms	50	50	100.00
		spi_device_flash_all	7.649m	130.783ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	27.900s	5.978ms	50	50	100.00
		spi_device_flash_all	7.649m	130.783ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	27.900s	5.978ms	50	50	100.00
		spi_device_flash_all	7.649m	130.783ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	27.900s	5.978ms	50	50	100.00
		spi_device_flash_all	7.649m	130.783ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	27.900s	5.978ms	50	50	100.00
		spi_device_flash_all	7.649m	130.783ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	36.850s	56.848ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.017m	31.224ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.017m	31.224ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.017m	31.224ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.090m	34.867ms	50	50	100.00
		spi_device_read_buffer_direct	18.530s	1.499ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.017m	31.224ms	50	50	100.00
		spi_device_flash_all	7.649m	130.783ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	7.649m	130.783ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	7.649m	130.783ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	24.870s	17.070ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	24.870s	17.070ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	11.332m	267.696ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	12.543m	364.989ms	50	50	100.00
V2	stress_all	spi_device_stress_all	34.356m	858.541ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.790s	25.079us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.850s	14.520us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.470s	260.869us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.470s	260.869us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.300s	23.368us	5	5	100.00
		spi_device_csr_rw	2.860s	181.937us	20	20	100.00
		spi_device_csr_aliasing	9.090s	424.913us	5	5	100.00
		spi_device_same_csr_outstanding	4.190s	878.169us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.300s	23.368us	5	5	100.00
		spi_device_csr_rw	2.860s	181.937us	20	20	100.00
		spi_device_csr_aliasing	9.090s	424.913us	5	5	100.00
		spi_device_same_csr_outstanding	4.190s	878.169us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.180s	329.044us	5	5	100.00
		spi_device_tl_intg_err	22.940s	7.663ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	22.940s	7.663ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	7.591m	64.442ms	50	50	100.00
		TOTAL			1151	1151	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	98.45	94.08	98.62	89.36	97.29	95.43	99.26

Past Results

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