SPI_DEVICE/2P Simulation Results

Sunday August 04 2024 23:02:21 UTC

GitHub Revision: c8985d6745

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107130591329296133632864610148388701578652631018704528920799220771546870921898

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	14.140m	426.519ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.480s	386.899us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.710s	117.090us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	37.600s	2.723ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	24.270s	1.861ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.000s	119.492us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.710s	117.090us	20	20	100.00
		spi_device_csr_aliasing	24.270s	1.861ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.690s	11.013us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.190s	134.444us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.880s	34.040us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.200s	30.056us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.780s	41.479us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	9.350s	825.976us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	9.350s	825.976us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	27.300s	18.150ms	50	50	100.00
		spi_device_tpm_sts_read	1.120s	127.749us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	48.550s	32.657ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	37.250s	52.252ms	50	50	100.00
		spi_device_flash_all	8.010m	84.959ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	34.100s	22.444ms	50	50	100.00
		spi_device_flash_all	8.010m	84.959ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	34.100s	22.444ms	50	50	100.00
		spi_device_flash_all	8.010m	84.959ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	8.010m	84.959ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	25.100s	1.851ms	50	50	100.00
		spi_device_flash_all	8.010m	84.959ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	25.100s	1.851ms	50	50	100.00
		spi_device_flash_all	8.010m	84.959ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	25.100s	1.851ms	50	50	100.00
		spi_device_flash_all	8.010m	84.959ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	25.100s	1.851ms	50	50	100.00
		spi_device_flash_all	8.010m	84.959ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	25.100s	1.851ms	50	50	100.00
		spi_device_flash_all	8.010m	84.959ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	28.650s	15.891ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.551m	67.249ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.551m	67.249ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.551m	67.249ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.012m	4.448ms	50	50	100.00
		spi_device_read_buffer_direct	26.900s	2.248ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.551m	67.249ms	50	50	100.00
		spi_device_flash_all	8.010m	84.959ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	8.010m	84.959ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	8.010m	84.959ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	23.690s	3.189ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	23.690s	3.189ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	14.140m	426.519ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	10.633m	69.181ms	50	50	100.00
V2	stress_all	spi_device_stress_all	13.556m	81.699ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.790s	15.165us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.810s	15.678us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.460s	306.984us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.460s	306.984us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.480s	386.899us	5	5	100.00
		spi_device_csr_rw	2.710s	117.090us	20	20	100.00
		spi_device_csr_aliasing	24.270s	1.861ms	5	5	100.00
		spi_device_same_csr_outstanding	4.000s	339.358us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.480s	386.899us	5	5	100.00
		spi_device_csr_rw	2.710s	117.090us	20	20	100.00
		spi_device_csr_aliasing	24.270s	1.861ms	5	5	100.00
		spi_device_same_csr_outstanding	4.000s	339.358us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.640s	1.330ms	5	5	100.00
		spi_device_tl_intg_err	23.190s	9.277ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	23.190s	9.277ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	6.596m	54.046ms	50	50	100.00
		TOTAL			1151	1151	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	98.44	94.08	98.62	89.36	97.29	95.43	99.26

Past Results

• Latest
• 2024.08.04_06.57.26
• 2024.08.03_09.09.07
• 2024.08.02_08.21.39
• 2024.08.01_09.48.51
• 2024.07.31_09.16.35
• 2024.07.30_09.35.20
• 2024.07.29_08.00.25