SPI_DEVICE/2P Simulation Results

Monday August 05 2024 23:02:13 UTC

GitHub Revision: e4c5daa580

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 57478527486894479494471273459769404654835266620222125964939301612221385668501

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	7.952m	330.469ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.210s	201.130us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.750s	461.765us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	34.720s	9.362ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	22.780s	1.120ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.860s	248.173us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.750s	461.765us	20	20	100.00
		spi_device_csr_aliasing	22.780s	1.120ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.690s	10.190us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.170s	368.560us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.890s	61.180us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.160s	236.947us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.760s	17.055us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	9.200s	4.388ms	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	9.200s	4.388ms	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	20.770s	15.453ms	50	50	100.00
		spi_device_tpm_sts_read	0.990s	1.047ms	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	43.930s	25.163ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	35.320s	11.976ms	50	50	100.00
		spi_device_flash_all	6.094m	105.987ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	40.320s	62.208ms	50	50	100.00
		spi_device_flash_all	6.094m	105.987ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	40.320s	62.208ms	50	50	100.00
		spi_device_flash_all	6.094m	105.987ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	6.094m	105.987ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	27.060s	9.355ms	50	50	100.00
		spi_device_flash_all	6.094m	105.987ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	27.060s	9.355ms	50	50	100.00
		spi_device_flash_all	6.094m	105.987ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	27.060s	9.355ms	50	50	100.00
		spi_device_flash_all	6.094m	105.987ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	27.060s	9.355ms	50	50	100.00
		spi_device_flash_all	6.094m	105.987ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	27.060s	9.355ms	50	50	100.00
		spi_device_flash_all	6.094m	105.987ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	46.420s	19.648ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.226m	11.052ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.226m	11.052ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.226m	11.052ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.395m	13.045ms	50	50	100.00
		spi_device_read_buffer_direct	27.480s	4.519ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.226m	11.052ms	50	50	100.00
		spi_device_flash_all	6.094m	105.987ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	6.094m	105.987ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	6.094m	105.987ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	26.980s	2.047ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	26.980s	2.047ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	7.952m	330.469ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	13.244m	80.596ms	50	50	100.00
V2	stress_all	spi_device_stress_all	15.469m	570.145ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.810s	43.645us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.830s	15.919us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.260s	455.136us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.260s	455.136us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.210s	201.130us	5	5	100.00
		spi_device_csr_rw	2.750s	461.765us	20	20	100.00
		spi_device_csr_aliasing	22.780s	1.120ms	5	5	100.00
		spi_device_same_csr_outstanding	4.470s	432.523us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.210s	201.130us	5	5	100.00
		spi_device_csr_rw	2.750s	461.765us	20	20	100.00
		spi_device_csr_aliasing	22.780s	1.120ms	5	5	100.00
		spi_device_same_csr_outstanding	4.470s	432.523us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.290s	170.148us	5	5	100.00
		spi_device_tl_intg_err	19.560s	820.576us	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	19.560s	820.576us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	6.261m	225.150ms	50	50	100.00
		TOTAL			1151	1151	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	98.45	94.10	98.62	89.36	97.29	95.43	99.26

Past Results

• Latest
• 2024.08.05_11.09.40
• 2024.08.04_06.57.26
• 2024.08.03_09.09.07
• 2024.08.02_08.21.39
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