SPI_DEVICE/2P Simulation Results

Tuesday August 06 2024 23:02:29 UTC

GitHub Revision: `5fd4ecc0fc`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 56304622830272859824235340993951659280265419461975949533183046575604373639200

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	10.305m	163.866ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.360s	82.089us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.880s	222.816us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	25.000s	6.438ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	16.720s	4.137ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.930s	135.598us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.880s	222.816us	20	20	100.00
		spi_device_csr_aliasing	16.720s	4.137ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.690s	11.860us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.890s	101.183us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.850s	25.235us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.310s	105.424us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.800s	17.503us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	10.650s	1.096ms	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	10.650s	1.096ms	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	20.470s	7.511ms	50	50	100.00
		spi_device_tpm_sts_read	1.080s	113.086us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.048m	74.411ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	17.430s	20.766ms	50	50	100.00
		spi_device_flash_all	8.096m	288.256ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	33.970s	21.798ms	50	50	100.00
		spi_device_flash_all	8.096m	288.256ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	33.970s	21.798ms	50	50	100.00
		spi_device_flash_all	8.096m	288.256ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	8.096m	288.256ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	44.130s	4.519ms	50	50	100.00
		spi_device_flash_all	8.096m	288.256ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	44.130s	4.519ms	50	50	100.00
		spi_device_flash_all	8.096m	288.256ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	44.130s	4.519ms	50	50	100.00
		spi_device_flash_all	8.096m	288.256ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	44.130s	4.519ms	50	50	100.00
		spi_device_flash_all	8.096m	288.256ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	44.130s	4.519ms	50	50	100.00
		spi_device_flash_all	8.096m	288.256ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	30.850s	11.159ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.168m	38.715ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.168m	38.715ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.168m	38.715ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	52.570s	8.813ms	50	50	100.00
		spi_device_read_buffer_direct	14.530s	4.890ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.168m	38.715ms	50	50	100.00
		spi_device_flash_all	8.096m	288.256ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	8.096m	288.256ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	8.096m	288.256ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	28.140s	11.600ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	28.140s	11.600ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	10.305m	163.866ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	11.228m	147.124ms	50	50	100.00
V2	stress_all	spi_device_stress_all	23.409m	299.288ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.850s	44.587us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.850s	23.102us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.290s	196.757us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.290s	196.757us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.360s	82.089us	5	5	100.00
		spi_device_csr_rw	2.880s	222.816us	20	20	100.00
		spi_device_csr_aliasing	16.720s	4.137ms	5	5	100.00
		spi_device_same_csr_outstanding	4.240s	63.426us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.360s	82.089us	5	5	100.00
		spi_device_csr_rw	2.880s	222.816us	20	20	100.00
		spi_device_csr_aliasing	16.720s	4.137ms	5	5	100.00
		spi_device_same_csr_outstanding	4.240s	63.426us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.150s	57.804us	5	5	100.00
		spi_device_tl_intg_err	21.650s	2.578ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	21.650s	2.578ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	7.263m	252.764ms	48	50	96.00
		TOTAL			1149	1151	99.83

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.05	98.44	94.10	98.62	89.36	97.28	95.29	99.26

Failure Buckets

UVM_ERROR (spi_device_pass_base_vseq.sv:704) [spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be * has 1 failures:

Test spi_device_flash_mode_ignore_cmds has 1 failures.

10.spi_device_flash_mode_ignore_cmds.104749275016875924296442682403423006767516021010193192839216745132570439796499
Line 292, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/10.spi_device_flash_mode_ignore_cmds/latest/run.log

  UVM_ERROR @ 75886919882 ps: (spi_device_pass_base_vseq.sv:704) [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  tl_ul_fuzzy_flash_status_q[i] = 0xcbe320
  UVM_INFO @ 82211123807 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 10/11
  UVM_INFO @ 82255554124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Job spi_device_2p-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test spi_device_flash_mode_ignore_cmds has 1 failures.
  - 25.spi_device_flash_mode_ignore_cmds.87573307043505098510261654672277594636700096410013106312621108747505060662919
    Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/25.spi_device_flash_mode_ignore_cmds/latest/run.log
```
  Job ID: smart:6d366d12-0644-4bf0-8e45-5a46278ac49c
```