SPI_DEVICE/2P Simulation Results

Wednesday August 07 2024 23:02:33 UTC

GitHub Revision: bbf435ceff

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 6888687353677204195542416712589698377810102273194685652880785004967849651007

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	15.256m	1.057s	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.460s	47.970us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.190s	273.259us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	36.220s	3.070ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	20.320s	302.568us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.670s	55.973us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.190s	273.259us	20	20	100.00
		spi_device_csr_aliasing	20.320s	302.568us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.700s	19.109us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.810s	67.954us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.850s	18.306us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.200s	62.024us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.780s	16.194us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	9.170s	602.050us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	9.170s	602.050us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	24.790s	8.608ms	50	50	100.00
		spi_device_tpm_sts_read	1.100s	1.537ms	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.063m	11.900ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	27.970s	36.146ms	50	50	100.00
		spi_device_flash_all	9.141m	216.723ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	31.160s	11.022ms	50	50	100.00
		spi_device_flash_all	9.141m	216.723ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	31.160s	11.022ms	50	50	100.00
		spi_device_flash_all	9.141m	216.723ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	9.141m	216.723ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	34.160s	16.108ms	50	50	100.00
		spi_device_flash_all	9.141m	216.723ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	34.160s	16.108ms	50	50	100.00
		spi_device_flash_all	9.141m	216.723ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	34.160s	16.108ms	50	50	100.00
		spi_device_flash_all	9.141m	216.723ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	34.160s	16.108ms	50	50	100.00
		spi_device_flash_all	9.141m	216.723ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	34.160s	16.108ms	50	50	100.00
		spi_device_flash_all	9.141m	216.723ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	36.900s	58.100ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.171m	31.520ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.171m	31.520ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.171m	31.520ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.662m	7.546ms	50	50	100.00
		spi_device_read_buffer_direct	19.250s	5.510ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.171m	31.520ms	50	50	100.00
		spi_device_flash_all	9.141m	216.723ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	9.141m	216.723ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	9.141m	216.723ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	29.640s	2.078ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	29.640s	2.078ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	15.256m	1.057s	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	17.664m	98.567ms	50	50	100.00
V2	stress_all	spi_device_stress_all	13.349m	464.683ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.810s	38.831us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.810s	20.146us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.640s	317.642us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.640s	317.642us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.460s	47.970us	5	5	100.00
		spi_device_csr_rw	3.190s	273.259us	20	20	100.00
		spi_device_csr_aliasing	20.320s	302.568us	5	5	100.00
		spi_device_same_csr_outstanding	4.320s	1.083ms	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.460s	47.970us	5	5	100.00
		spi_device_csr_rw	3.190s	273.259us	20	20	100.00
		spi_device_csr_aliasing	20.320s	302.568us	5	5	100.00
		spi_device_same_csr_outstanding	4.320s	1.083ms	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.280s	167.672us	5	5	100.00
		spi_device_tl_intg_err	21.810s	816.397us	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	21.810s	816.397us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	7.208m	121.351ms	49	50	98.00
		TOTAL			1150	1151	99.91

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.06	98.45	94.08	98.62	89.36	97.29	95.43	99.21

Failure Buckets

• UVM_ERROR (spi_device_pass_base_vseq.sv:704) [spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be * has 1 failures:
  • Test spi_device_flash_mode_ignore_cmds has 1 failures.

    • 13.spi_device_flash_mode_ignore_cmds.113911774965297361872856438378630587444470966962205197493888048186224856733067
      Line 269, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/13.spi_device_flash_mode_ignore_cmds/latest/run.log

        UVM_ERROR @ 45778474329 ps: (spi_device_pass_base_vseq.sv:704) [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
        tl_ul_fuzzy_flash_status_q[i] = 0x56c0ae
        UVM_INFO @ 47180610546 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 3/6
        UVM_INFO @ 47180610546 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 4/6
        tl_ul_fuzzy_flash_status_q[i] = 0x74b6dc
      

Past Results

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