SPI_DEVICE/2P Simulation Results

Thursday August 08 2024 23:02:08 UTC

GitHub Revision: 3707c48f56

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 96859198578252641766218135484681220968075710602306197013001824903089223290045

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	9.610m	60.121ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.460s	461.336us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.020s	124.429us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	38.260s	2.791ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	17.410s	3.321ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.870s	514.919us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.020s	124.429us	20	20	100.00
		spi_device_csr_aliasing	17.410s	3.321ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.680s	157.717us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.230s	481.391us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.880s	21.405us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.130s	24.820us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.740s	15.118us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	10.000s	200.718us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	10.000s	200.718us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	28.160s	11.005ms	50	50	100.00
		spi_device_tpm_sts_read	1.060s	117.381us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	52.430s	43.984ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	23.020s	120.731ms	50	50	100.00
		spi_device_flash_all	8.153m	65.844ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	45.100s	73.321ms	50	50	100.00
		spi_device_flash_all	8.153m	65.844ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	45.100s	73.321ms	50	50	100.00
		spi_device_flash_all	8.153m	65.844ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	8.153m	65.844ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	32.200s	46.757ms	50	50	100.00
		spi_device_flash_all	8.153m	65.844ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	32.200s	46.757ms	50	50	100.00
		spi_device_flash_all	8.153m	65.844ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	32.200s	46.757ms	50	50	100.00
		spi_device_flash_all	8.153m	65.844ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	32.200s	46.757ms	50	50	100.00
		spi_device_flash_all	8.153m	65.844ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	32.200s	46.757ms	50	50	100.00
		spi_device_flash_all	8.153m	65.844ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	37.480s	20.218ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	3.069m	69.047ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	3.069m	69.047ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	3.069m	69.047ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.080m	25.202ms	49	50	98.00
		spi_device_read_buffer_direct	23.360s	2.036ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	3.069m	69.047ms	50	50	100.00
		spi_device_flash_all	8.153m	65.844ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	8.153m	65.844ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	8.153m	65.844ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	33.690s	4.331ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	33.690s	4.331ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	9.610m	60.121ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	11.121m	306.653ms	50	50	100.00
V2	stress_all	spi_device_stress_all	15.745m	387.111ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.820s	113.459us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.810s	17.332us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.730s	932.536us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.730s	932.536us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.460s	461.336us	5	5	100.00
		spi_device_csr_rw	3.020s	124.429us	20	20	100.00
		spi_device_csr_aliasing	17.410s	3.321ms	5	5	100.00
		spi_device_same_csr_outstanding	4.120s	644.204us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.460s	461.336us	5	5	100.00
		spi_device_csr_rw	3.020s	124.429us	20	20	100.00
		spi_device_csr_aliasing	17.410s	3.321ms	5	5	100.00
		spi_device_same_csr_outstanding	4.120s	644.204us	20	20	100.00
V2		TOTAL			960	961	99.90
V2S	tl_intg_err	spi_device_sec_cm	1.140s	87.539us	5	5	100.00
		spi_device_tl_intg_err	21.680s	1.170ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	21.680s	1.170ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	8.473m	229.689ms	50	50	100.00
		TOTAL			1150	1151	99.91

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	98.44	94.08	98.62	89.36	97.28	95.43	99.26

Failure Buckets

• UVM_ERROR (spi_device_scoreboard.sv:2338) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare ReadbufWatermark mismatch, act (*) != exp * has 1 failures:
  • Test spi_device_flash_mode has 1 failures.

    • 22.spi_device_flash_mode.50792376692325114623970531270411572380793933273695714748286648262694977818369
      Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/22.spi_device_flash_mode/latest/run.log

        UVM_ERROR @  26748538 ps: (spi_device_scoreboard.sv:2338) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufWatermark mismatch, act (0x1) != exp 0
        UVM_ERROR @ 2339889818 ps: (spi_device_scoreboard.sv:2803) [uvm_test_top.env.scoreboard] Check failed |(intr_trigger_pending & interrupt_mask) == 0 (1 [0x1] vs 0 [0x0])
        UVM_INFO @ 2339889818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
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