SPI_DEVICE/2P Simulation Results

Friday August 09 2024 23:02:07 UTC

GitHub Revision: 07b417ef03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 39866585070056138360117926942905553094756411441088058786676399955088054585836

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	7.805m	195.119ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.420s	100.041us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.690s	41.697us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	32.740s	527.272us	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	22.100s	3.759ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.910s	210.146us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.690s	41.697us	20	20	100.00
		spi_device_csr_aliasing	22.100s	3.759ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.690s	41.801us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.760s	52.472us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.820s	67.559us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.160s	60.792us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.740s	38.336us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	5.360s	125.390us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	5.360s	125.390us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	23.590s	34.233ms	50	50	100.00
		spi_device_tpm_sts_read	1.060s	456.543us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	45.980s	32.357ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	37.090s	49.123ms	50	50	100.00
		spi_device_flash_all	8.489m	117.904ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	47.260s	33.004ms	50	50	100.00
		spi_device_flash_all	8.489m	117.904ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	47.260s	33.004ms	50	50	100.00
		spi_device_flash_all	8.489m	117.904ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	8.489m	117.904ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	36.620s	3.035ms	50	50	100.00
		spi_device_flash_all	8.489m	117.904ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	36.620s	3.035ms	50	50	100.00
		spi_device_flash_all	8.489m	117.904ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	36.620s	3.035ms	50	50	100.00
		spi_device_flash_all	8.489m	117.904ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	36.620s	3.035ms	50	50	100.00
		spi_device_flash_all	8.489m	117.904ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	36.620s	3.035ms	50	50	100.00
		spi_device_flash_all	8.489m	117.904ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	44.070s	14.309ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.140m	43.098ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.140m	43.098ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.140m	43.098ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.017m	6.487ms	50	50	100.00
		spi_device_read_buffer_direct	20.420s	9.051ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.140m	43.098ms	50	50	100.00
		spi_device_flash_all	8.489m	117.904ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	8.489m	117.904ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	8.489m	117.904ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	25.020s	2.071ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	25.020s	2.071ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	7.805m	195.119ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	12.050m	73.788ms	50	50	100.00
V2	stress_all	spi_device_stress_all	14.808m	328.299ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.760s	14.582us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.810s	15.171us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.970s	533.541us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.970s	533.541us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.420s	100.041us	5	5	100.00
		spi_device_csr_rw	2.690s	41.697us	20	20	100.00
		spi_device_csr_aliasing	22.100s	3.759ms	5	5	100.00
		spi_device_same_csr_outstanding	4.410s	659.418us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.420s	100.041us	5	5	100.00
		spi_device_csr_rw	2.690s	41.697us	20	20	100.00
		spi_device_csr_aliasing	22.100s	3.759ms	5	5	100.00
		spi_device_same_csr_outstanding	4.410s	659.418us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.570s	1.471ms	5	5	100.00
		spi_device_tl_intg_err	22.600s	3.200ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	22.600s	3.200ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	6.517m	209.609ms	50	50	100.00
		TOTAL			1151	1151	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.06	98.44	94.08	98.62	89.36	97.28	95.43	99.21

Past Results

• Latest
• 2024.08.09_08.02.41
• 2024.08.08_09.16.19
• 2024.08.07_09.09.59
• 2024.08.06_09.39.05
• 2024.08.05_11.09.40
• 2024.08.04_06.57.26
• 2024.08.03_09.09.07