SPI_DEVICE/2P Simulation Results

Saturday August 10 2024 23:02:23 UTC

GitHub Revision: 07b417ef03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2196818177928134427831197337249851347498377272679561983541244979366753055772

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	11.033m	73.980ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.210s	40.620us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.760s	101.314us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	39.400s	11.244ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	23.770s	1.827ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.000s	143.960us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.760s	101.314us	20	20	100.00
		spi_device_csr_aliasing	23.770s	1.827ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.660s	22.735us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.820s	52.839us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.870s	18.911us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.170s	60.870us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.740s	42.835us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	10.330s	239.908us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	10.330s	239.908us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	20.980s	8.177ms	50	50	100.00
		spi_device_tpm_sts_read	1.060s	104.238us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	44.050s	9.977ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	39.240s	13.523ms	50	50	100.00
		spi_device_flash_all	7.202m	238.927ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	33.430s	12.951ms	50	50	100.00
		spi_device_flash_all	7.202m	238.927ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	33.430s	12.951ms	50	50	100.00
		spi_device_flash_all	7.202m	238.927ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	7.202m	238.927ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	25.240s	2.739ms	50	50	100.00
		spi_device_flash_all	7.202m	238.927ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	25.240s	2.739ms	50	50	100.00
		spi_device_flash_all	7.202m	238.927ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	25.240s	2.739ms	50	50	100.00
		spi_device_flash_all	7.202m	238.927ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	25.240s	2.739ms	50	50	100.00
		spi_device_flash_all	7.202m	238.927ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	25.240s	2.739ms	50	50	100.00
		spi_device_flash_all	7.202m	238.927ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	22.680s	9.764ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.084m	44.774ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.084m	44.774ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.084m	44.774ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.107m	20.240ms	50	50	100.00
		spi_device_read_buffer_direct	15.090s	2.093ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.084m	44.774ms	50	50	100.00
		spi_device_flash_all	7.202m	238.927ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	7.202m	238.927ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	7.202m	238.927ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	28.740s	6.136ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	28.740s	6.136ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	11.033m	73.980ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	7.288m	44.864ms	50	50	100.00
V2	stress_all	spi_device_stress_all	8.028m	52.033ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.800s	51.802us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.790s	27.138us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.590s	395.539us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.590s	395.539us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.210s	40.620us	5	5	100.00
		spi_device_csr_rw	2.760s	101.314us	20	20	100.00
		spi_device_csr_aliasing	23.770s	1.827ms	5	5	100.00
		spi_device_same_csr_outstanding	4.400s	297.033us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.210s	40.620us	5	5	100.00
		spi_device_csr_rw	2.760s	101.314us	20	20	100.00
		spi_device_csr_aliasing	23.770s	1.827ms	5	5	100.00
		spi_device_same_csr_outstanding	4.400s	297.033us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.180s	81.520us	5	5	100.00
		spi_device_tl_intg_err	22.370s	4.050ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	22.370s	4.050ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	58.320m	1.500s	47	50	94.00
		TOTAL			1148	1151	99.74

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.06	98.44	94.10	98.62	89.36	97.29	95.43	99.21

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:

  • Test spi_device_flash_mode_ignore_cmds has 2 failures.

    • 16.spi_device_flash_mode_ignore_cmds.37488916256415991644888088867320209958866943633874054626685519982837539850079
      Line 261, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/16.spi_device_flash_mode_ignore_cmds/latest/run.log

        UVM_FATAL @ 1500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1500000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 43.spi_device_flash_mode_ignore_cmds.73784214098482037941771243241422266719090646838283422715082809483110083112201
      Line 269, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/43.spi_device_flash_mode_ignore_cmds/latest/run.log

        UVM_FATAL @ 1500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1500000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job spi_device_2p-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:

  • Test spi_device_flash_mode_ignore_cmds has 1 failures.

    • 23.spi_device_flash_mode_ignore_cmds.86866302961876457489033615068206068298842717239309117973727127814347704651303
      Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/23.spi_device_flash_mode_ignore_cmds/latest/run.log

        Job ID: smart:e8a12037-84f7-4d7c-bfa5-d8e1c7860393
      

Past Results

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