SPI_DEVICE/2P Simulation Results

Sunday August 11 2024 23:02:21 UTC

GitHub Revision: 07b417ef03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 6142445146730822936893044599112392910298048088673599708943858624824800218011

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	11.814m	72.373ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.420s	47.714us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.800s	1.363ms	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	32.000s	3.479ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	23.710s	2.217ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.940s	163.022us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.800s	1.363ms	20	20	100.00
		spi_device_csr_aliasing	23.710s	2.217ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.670s	13.410us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.290s	197.445us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.850s	27.931us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.160s	28.889us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.740s	16.991us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	5.180s	244.466us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	5.180s	244.466us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	27.680s	55.035ms	50	50	100.00
		spi_device_tpm_sts_read	1.030s	176.138us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	47.460s	19.694ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	37.440s	57.923ms	50	50	100.00
		spi_device_flash_all	8.711m	306.639ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	37.450s	13.464ms	50	50	100.00
		spi_device_flash_all	8.711m	306.639ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	37.450s	13.464ms	50	50	100.00
		spi_device_flash_all	8.711m	306.639ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	8.711m	306.639ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	33.590s	11.948ms	50	50	100.00
		spi_device_flash_all	8.711m	306.639ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	33.590s	11.948ms	50	50	100.00
		spi_device_flash_all	8.711m	306.639ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	33.590s	11.948ms	50	50	100.00
		spi_device_flash_all	8.711m	306.639ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	33.590s	11.948ms	50	50	100.00
		spi_device_flash_all	8.711m	306.639ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	33.590s	11.948ms	50	50	100.00
		spi_device_flash_all	8.711m	306.639ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	39.900s	12.101ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.772m	63.992ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.772m	63.992ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.772m	63.992ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	49.290s	24.629ms	50	50	100.00
		spi_device_read_buffer_direct	20.030s	11.161ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.772m	63.992ms	50	50	100.00
		spi_device_flash_all	8.711m	306.639ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	8.711m	306.639ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	8.711m	306.639ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	23.870s	7.321ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	23.870s	7.321ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	11.814m	72.373ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	12.422m	78.918ms	50	50	100.00
V2	stress_all	spi_device_stress_all	14.044m	108.541ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.820s	13.228us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.820s	30.377us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	6.060s	1.083ms	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	6.060s	1.083ms	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.420s	47.714us	5	5	100.00
		spi_device_csr_rw	2.800s	1.363ms	20	20	100.00
		spi_device_csr_aliasing	23.710s	2.217ms	5	5	100.00
		spi_device_same_csr_outstanding	4.350s	202.948us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.420s	47.714us	5	5	100.00
		spi_device_csr_rw	2.800s	1.363ms	20	20	100.00
		spi_device_csr_aliasing	23.710s	2.217ms	5	5	100.00
		spi_device_same_csr_outstanding	4.350s	202.948us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.450s	207.306us	5	5	100.00
		spi_device_tl_intg_err	21.650s	1.681ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	21.650s	1.681ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	5.621m	185.215ms	50	50	100.00
		TOTAL			1151	1151	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.06	98.44	94.08	98.62	89.36	97.28	95.43	99.21

Past Results

• Latest
• 2024.08.11_08.26.48
• 2024.08.10_08.32.42
• 2024.08.09_08.02.41
• 2024.08.08_09.16.19
• 2024.08.07_09.09.59
• 2024.08.06_09.39.05
• 2024.08.05_11.09.40