SPI_DEVICE/2P Simulation Results

Monday August 12 2024 23:02:30 UTC

GitHub Revision: c082b8981f

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107262934208806092150901079363789224644653433402469901409990667510497383888850

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	12.075m	151.588ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.380s	74.286us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.520s	75.818us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	36.970s	1.883ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	16.740s	2.921ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.610s	304.037us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.520s	75.818us	20	20	100.00
		spi_device_csr_aliasing	16.740s	2.921ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.690s	11.911us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.220s	61.443us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.850s	282.802us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.100s	107.865us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.730s	174.686us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	7.880s	175.456us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	7.880s	175.456us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	20.820s	30.578ms	50	50	100.00
		spi_device_tpm_sts_read	1.140s	156.331us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	42.410s	17.299ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	36.650s	50.964ms	50	50	100.00
		spi_device_flash_all	8.244m	304.474ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	50.450s	80.586ms	50	50	100.00
		spi_device_flash_all	8.244m	304.474ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	50.450s	80.586ms	50	50	100.00
		spi_device_flash_all	8.244m	304.474ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	8.244m	304.474ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	28.120s	13.163ms	50	50	100.00
		spi_device_flash_all	8.244m	304.474ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	28.120s	13.163ms	50	50	100.00
		spi_device_flash_all	8.244m	304.474ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	28.120s	13.163ms	50	50	100.00
		spi_device_flash_all	8.244m	304.474ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	28.120s	13.163ms	50	50	100.00
		spi_device_flash_all	8.244m	304.474ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	28.120s	13.163ms	50	50	100.00
		spi_device_flash_all	8.244m	304.474ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	22.100s	7.213ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.523m	57.404ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.523m	57.404ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.523m	57.404ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.168m	4.696ms	50	50	100.00
		spi_device_read_buffer_direct	20.190s	8.014ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.523m	57.404ms	50	50	100.00
		spi_device_flash_all	8.244m	304.474ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	8.244m	304.474ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	8.244m	304.474ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	24.550s	3.975ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	24.550s	3.975ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	12.075m	151.588ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	10.388m	73.942ms	50	50	100.00
V2	stress_all	spi_device_stress_all	18.460m	1.720s	50	50	100.00
V2	alert_test	spi_device_alert_test	0.780s	14.017us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.780s	96.993us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.500s	241.803us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.500s	241.803us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.380s	74.286us	5	5	100.00
		spi_device_csr_rw	2.520s	75.818us	20	20	100.00
		spi_device_csr_aliasing	16.740s	2.921ms	5	5	100.00
		spi_device_same_csr_outstanding	4.190s	151.894us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.380s	74.286us	5	5	100.00
		spi_device_csr_rw	2.520s	75.818us	20	20	100.00
		spi_device_csr_aliasing	16.740s	2.921ms	5	5	100.00
		spi_device_same_csr_outstanding	4.190s	151.894us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.210s	350.845us	5	5	100.00
		spi_device_tl_intg_err	22.190s	9.178ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	22.190s	9.178ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	8.603m	75.491ms	50	50	100.00
		TOTAL			1151	1151	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.06	98.44	94.08	98.62	89.36	97.28	95.43	99.21

Past Results

• Latest
• 2024.08.12_08.40.55
• 2024.08.11_08.26.48
• 2024.08.10_08.32.42
• 2024.08.09_08.02.41
• 2024.08.08_09.16.19
• 2024.08.07_09.09.59
• 2024.08.06_09.39.05