SPI_DEVICE/2P Simulation Results

Tuesday August 13 2024 23:04:47 UTC

GitHub Revision: 098010d125

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 12185085088694708177096441863424670920996379189869351644310607217057882846251

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	11.025m	298.357ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.510s	48.620us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.570s	324.869us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	36.150s	1.881ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	25.310s	2.519ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.130s	306.964us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.570s	324.869us	20	20	100.00
		spi_device_csr_aliasing	25.310s	2.519ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.700s	13.270us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.120s	241.848us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.870s	66.649us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.180s	117.286us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.780s	28.371us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	7.100s	494.255us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	7.100s	494.255us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	21.600s	14.347ms	50	50	100.00
		spi_device_tpm_sts_read	1.090s	92.657us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	42.320s	6.274ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	43.610s	17.288ms	50	50	100.00
		spi_device_flash_all	7.356m	947.387ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	42.210s	13.451ms	50	50	100.00
		spi_device_flash_all	7.356m	947.387ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	42.210s	13.451ms	50	50	100.00
		spi_device_flash_all	7.356m	947.387ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	7.356m	947.387ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	37.260s	3.919ms	50	50	100.00
		spi_device_flash_all	7.356m	947.387ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	37.260s	3.919ms	50	50	100.00
		spi_device_flash_all	7.356m	947.387ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	37.260s	3.919ms	50	50	100.00
		spi_device_flash_all	7.356m	947.387ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	37.260s	3.919ms	50	50	100.00
		spi_device_flash_all	7.356m	947.387ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	37.260s	3.919ms	50	50	100.00
		spi_device_flash_all	7.356m	947.387ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	31.750s	40.087ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.321m	48.089ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.321m	48.089ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.321m	48.089ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	52.030s	21.723ms	50	50	100.00
		spi_device_read_buffer_direct	22.330s	3.442ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.321m	48.089ms	50	50	100.00
		spi_device_flash_all	7.356m	947.387ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	7.356m	947.387ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	7.356m	947.387ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	32.830s	4.114ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	32.830s	4.114ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	11.025m	298.357ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	10.018m	70.263ms	50	50	100.00
V2	stress_all	spi_device_stress_all	17.984m	114.400ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.790s	16.010us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.820s	30.943us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	7.340s	300.763us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	7.340s	300.763us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.510s	48.620us	5	5	100.00
		spi_device_csr_rw	2.570s	324.869us	20	20	100.00
		spi_device_csr_aliasing	25.310s	2.519ms	5	5	100.00
		spi_device_same_csr_outstanding	4.280s	164.828us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.510s	48.620us	5	5	100.00
		spi_device_csr_rw	2.570s	324.869us	20	20	100.00
		spi_device_csr_aliasing	25.310s	2.519ms	5	5	100.00
		spi_device_same_csr_outstanding	4.280s	164.828us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.270s	90.035us	5	5	100.00
		spi_device_tl_intg_err	24.470s	1.068ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	24.470s	1.068ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	10.404m	309.116ms	49	50	98.00
		TOTAL			1150	1151	99.91

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	98.44	94.08	98.62	89.36	97.28	95.43	99.26

Failure Buckets

• UVM_ERROR (spi_device_pass_base_vseq.sv:704) [spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be * has 1 failures:
  • Test spi_device_flash_mode_ignore_cmds has 1 failures.

    • 4.spi_device_flash_mode_ignore_cmds.97666310932091107875093968709016683049836305162284834827776013269478440367057
      Line 277, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/4.spi_device_flash_mode_ignore_cmds/latest/run.log

        UVM_ERROR @ 29581341708 ps: (spi_device_pass_base_vseq.sv:704) [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
        tl_ul_fuzzy_flash_status_q[i] = 0xc2fb48
        tl_ul_fuzzy_flash_status_q[i] = 0x8d2528
        UVM_INFO @ 33021191740 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 4/5
        UVM_INFO @ 33048334420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
      

Past Results

• Latest
• 2024.08.13_08.11.43
• 2024.08.12_08.40.55
• 2024.08.11_08.26.48
• 2024.08.10_08.32.42
• 2024.08.09_08.02.41
• 2024.08.08_09.16.19
• 2024.08.07_09.09.59