SPI_DEVICE/2P Simulation Results

Wednesday August 14 2024 23:02:33 UTC

GitHub Revision: 584c3d46af

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 75916000169703078066460267353397937307391759551032957123310220571514951708138

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	12.037m	72.609ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.210s	111.226us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.800s	122.146us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	37.800s	2.858ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	23.000s	2.761ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.030s	77.747us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.800s	122.146us	20	20	100.00
		spi_device_csr_aliasing	23.000s	2.761ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.680s	11.056us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.130s	27.879us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.830s	74.972us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.120s	35.654us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.740s	34.860us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	11.520s	252.659us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	11.520s	252.659us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	20.870s	9.034ms	50	50	100.00
		spi_device_tpm_sts_read	1.050s	129.367us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	41.480s	7.417ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	38.120s	13.561ms	50	50	100.00
		spi_device_flash_all	10.134m	103.516ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	31.490s	23.141ms	50	50	100.00
		spi_device_flash_all	10.134m	103.516ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	31.490s	23.141ms	50	50	100.00
		spi_device_flash_all	10.134m	103.516ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	10.134m	103.516ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	38.010s	3.239ms	50	50	100.00
		spi_device_flash_all	10.134m	103.516ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	38.010s	3.239ms	50	50	100.00
		spi_device_flash_all	10.134m	103.516ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	38.010s	3.239ms	50	50	100.00
		spi_device_flash_all	10.134m	103.516ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	38.010s	3.239ms	50	50	100.00
		spi_device_flash_all	10.134m	103.516ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	38.010s	3.239ms	50	50	100.00
		spi_device_flash_all	10.134m	103.516ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	44.810s	103.934ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.079m	15.981ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.079m	15.981ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.079m	15.981ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	56.220s	18.744ms	50	50	100.00
		spi_device_read_buffer_direct	17.640s	7.067ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.079m	15.981ms	50	50	100.00
		spi_device_flash_all	10.134m	103.516ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	10.134m	103.516ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	10.134m	103.516ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	29.910s	2.620ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	29.910s	2.620ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	12.037m	72.609ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	11.049m	69.301ms	50	50	100.00
V2	stress_all	spi_device_stress_all	19.440m	2.379s	50	50	100.00
V2	alert_test	spi_device_alert_test	0.790s	46.420us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.790s	28.657us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.690s	250.843us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.690s	250.843us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.210s	111.226us	5	5	100.00
		spi_device_csr_rw	2.800s	122.146us	20	20	100.00
		spi_device_csr_aliasing	23.000s	2.761ms	5	5	100.00
		spi_device_same_csr_outstanding	4.560s	495.796us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.210s	111.226us	5	5	100.00
		spi_device_csr_rw	2.800s	122.146us	20	20	100.00
		spi_device_csr_aliasing	23.000s	2.761ms	5	5	100.00
		spi_device_same_csr_outstanding	4.560s	495.796us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.210s	85.358us	5	5	100.00
		spi_device_tl_intg_err	23.650s	7.162ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	23.650s	7.162ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	31.707m	1.500s	49	50	98.00
		TOTAL			1150	1151	99.91

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	98.44	94.08	98.62	89.36	97.28	95.43	99.26

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test spi_device_flash_mode_ignore_cmds has 1 failures.

    • 22.spi_device_flash_mode_ignore_cmds.11148532943392784789539639870168077378448625999453850947238111628772605949518
      Line 308, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/22.spi_device_flash_mode_ignore_cmds/latest/run.log

        UVM_FATAL @ 1500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1500000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.08.14_08.45.51
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