SPI_DEVICE/2P Simulation Results

Thursday August 15 2024 23:02:21 UTC

GitHub Revision: `d09e282b26`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 47908880312501934977153450267828796412449789719488445881682136509150457490963

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	13.462m	84.066ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.320s	23.143us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.610s	368.702us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	34.230s	9.378ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	23.940s	14.021ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.030s	167.181us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.610s	368.702us	20	20	100.00
		spi_device_csr_aliasing	23.940s	14.021ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.670s	20.202us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.200s	287.600us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.870s	43.745us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.150s	46.867us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.750s	30.576us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	7.930s	185.722us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	7.930s	185.722us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	28.320s	9.036ms	50	50	100.00
		spi_device_tpm_sts_read	1.040s	99.279us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.148m	12.567ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	39.280s	53.616ms	50	50	100.00
		spi_device_flash_all	7.340m	185.451ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	39.160s	73.537ms	50	50	100.00
		spi_device_flash_all	7.340m	185.451ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	39.160s	73.537ms	50	50	100.00
		spi_device_flash_all	7.340m	185.451ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	7.340m	185.451ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	24.610s	31.453ms	50	50	100.00
		spi_device_flash_all	7.340m	185.451ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	24.610s	31.453ms	50	50	100.00
		spi_device_flash_all	7.340m	185.451ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	24.610s	31.453ms	50	50	100.00
		spi_device_flash_all	7.340m	185.451ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	24.610s	31.453ms	50	50	100.00
		spi_device_flash_all	7.340m	185.451ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	24.610s	31.453ms	50	50	100.00
		spi_device_flash_all	7.340m	185.451ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	34.830s	50.458ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.703m	36.320ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.703m	36.320ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.703m	36.320ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.156m	12.584ms	50	50	100.00
		spi_device_read_buffer_direct	21.420s	1.560ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.703m	36.320ms	50	50	100.00
		spi_device_flash_all	7.340m	185.451ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	7.340m	185.451ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	7.340m	185.451ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	16.460s	1.340ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	16.460s	1.340ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	13.462m	84.066ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	9.518m	54.719ms	49	50	98.00
V2	stress_all	spi_device_stress_all	22.678m	286.461ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.820s	13.084us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.840s	118.693us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.830s	1.249ms	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.830s	1.249ms	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.320s	23.143us	5	5	100.00
		spi_device_csr_rw	2.610s	368.702us	20	20	100.00
		spi_device_csr_aliasing	23.940s	14.021ms	5	5	100.00
		spi_device_same_csr_outstanding	4.180s	913.928us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.320s	23.143us	5	5	100.00
		spi_device_csr_rw	2.610s	368.702us	20	20	100.00
		spi_device_csr_aliasing	23.940s	14.021ms	5	5	100.00
		spi_device_same_csr_outstanding	4.180s	913.928us	20	20	100.00
V2		TOTAL			960	961	99.90
V2S	tl_intg_err	spi_device_sec_cm	1.290s	105.532us	5	5	100.00
		spi_device_tl_intg_err	25.870s	4.619ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	25.870s	4.619ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	7.660m	71.279ms	49	50	98.00
		TOTAL			1149	1151	99.83

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	98.44	94.11	98.62	89.36	97.28	95.43	99.26

Failure Buckets

UVM_ERROR (spi_device_pass_base_vseq.sv:704) [spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be * has 1 failures:

Test spi_device_flash_mode_ignore_cmds has 1 failures.

28.spi_device_flash_mode_ignore_cmds.26842713853658941860562581361405296975736802665026662120457273705692060523282
Line 290, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/28.spi_device_flash_mode_ignore_cmds/latest/run.log

  UVM_ERROR @ 16490091379 ps: (spi_device_pass_base_vseq.sv:704) [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  tl_ul_fuzzy_flash_status_q[i] = 0x8fcd5c
  tl_ul_fuzzy_flash_status_q[i] = 0x9cddcc
  UVM_INFO @ 17048127846 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 12/14
  UVM_INFO @ 17048127846 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 13/14

UVM_ERROR (spi_device_pass_base_vseq.sv:704) [flash_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be * has 1 failures:

Test spi_device_flash_and_tpm_min_idle has 1 failures.

49.spi_device_flash_and_tpm_min_idle.29458482372685816165672923783848860761286212582565933591395720108512268824868
Line 302, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/49.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 8986532386 ps: (spi_device_pass_base_vseq.sv:704) [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  tl_ul_fuzzy_flash_status_q[i] = 0xb060b4
  UVM_INFO @ 9344997508 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 12/13
  UVM_INFO @ 9388636352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---