SPI_DEVICE/2P Simulation Results

Friday August 16 2024 23:02:10 UTC

GitHub Revision: `76588857da`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 107397868712693014844033025164446565408841343499325418676943424680076749785789

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	7.677m	223.360ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.490s	53.945us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.800s	573.509us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	34.470s	9.813ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	23.790s	919.846us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.160s	158.945us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.800s	573.509us	20	20	100.00
		spi_device_csr_aliasing	23.790s	919.846us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.690s	22.097us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.340s	57.920us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.870s	25.689us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.130s	27.026us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.740s	63.761us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	11.530s	3.217ms	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	11.530s	3.217ms	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	22.960s	8.463ms	50	50	100.00
		spi_device_tpm_sts_read	1.000s	81.808us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	46.360s	8.049ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	30.120s	19.735ms	50	50	100.00
		spi_device_flash_all	6.035m	101.061ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	27.810s	143.889ms	50	50	100.00
		spi_device_flash_all	6.035m	101.061ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	27.810s	143.889ms	50	50	100.00
		spi_device_flash_all	6.035m	101.061ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	6.035m	101.061ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	37.480s	8.766ms	50	50	100.00
		spi_device_flash_all	6.035m	101.061ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	37.480s	8.766ms	50	50	100.00
		spi_device_flash_all	6.035m	101.061ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	37.480s	8.766ms	50	50	100.00
		spi_device_flash_all	6.035m	101.061ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	37.480s	8.766ms	50	50	100.00
		spi_device_flash_all	6.035m	101.061ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	37.480s	8.766ms	50	50	100.00
		spi_device_flash_all	6.035m	101.061ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	35.110s	11.217ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.140m	74.889ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.140m	74.889ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.140m	74.889ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	2.081m	8.533ms	50	50	100.00
		spi_device_read_buffer_direct	23.320s	8.953ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.140m	74.889ms	50	50	100.00
		spi_device_flash_all	6.035m	101.061ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	6.035m	101.061ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	6.035m	101.061ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	31.280s	2.819ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	31.280s	2.819ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	7.677m	223.360ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	8.424m	102.579ms	49	50	98.00
V2	stress_all	spi_device_stress_all	16.434m	121.673ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.790s	14.428us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.840s	43.961us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	6.550s	781.894us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	6.550s	781.894us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.490s	53.945us	5	5	100.00
		spi_device_csr_rw	2.800s	573.509us	20	20	100.00
		spi_device_csr_aliasing	23.790s	919.846us	5	5	100.00
		spi_device_same_csr_outstanding	4.410s	307.526us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.490s	53.945us	5	5	100.00
		spi_device_csr_rw	2.800s	573.509us	20	20	100.00
		spi_device_csr_aliasing	23.790s	919.846us	5	5	100.00
		spi_device_same_csr_outstanding	4.410s	307.526us	20	20	100.00
V2		TOTAL			960	961	99.90
V2S	tl_intg_err	spi_device_sec_cm	1.160s	90.718us	5	5	100.00
		spi_device_tl_intg_err	22.980s	1.906ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	22.980s	1.906ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	7.719m	71.635ms	49	50	98.00
		TOTAL			1149	1151	99.83

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	98.44	94.08	98.62	89.36	97.28	95.43	99.26

Failure Buckets

UVM_WARNING (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "busy" while containing register "spi_device_reg_block.flash_status" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem. has 1 failures:

Test spi_device_flash_and_tpm_min_idle has 1 failures.

7.spi_device_flash_and_tpm_min_idle.56981662284855693871293373920671794153647885794959529430438538945309063999996
Line 275, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/7.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_WARNING @ 5029376840 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "busy" while containing register "spi_device_reg_block.flash_status" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 5029376840 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "wel" while containing register "spi_device_reg_block.flash_status" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 5029376840 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "status" while containing register "spi_device_reg_block.flash_status" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  tl_ul_fuzzy_flash_status_q[i] = 0xad6338
  tl_ul_fuzzy_flash_status_q[i] = 0xfd898

Job spi_device_2p-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test spi_device_flash_mode_ignore_cmds has 1 failures.
  - 24.spi_device_flash_mode_ignore_cmds.71924425072546861827851663945360944524116499356226205190406586427669857090063
    Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/24.spi_device_flash_mode_ignore_cmds/latest/run.log
```
  Job ID: smart:68d89aaa-53f3-47d6-a73e-5a78feaf8e32
```