SPI_DEVICE/2P Simulation Results

Saturday August 17 2024 23:02:17 UTC

GitHub Revision: 76588857da

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 94235727392619910305578226901221990521512464990339520078429467885466612377995

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_device_flash_and_tpm 14.146m 229.428ms 50 50 100.00
V1 csr_hw_reset spi_device_csr_hw_reset 1.390s 78.444us 5 5 100.00
V1 csr_rw spi_device_csr_rw 2.960s 101.554us 20 20 100.00
V1 csr_bit_bash spi_device_csr_bit_bash 40.070s 2.734ms 5 5 100.00
V1 csr_aliasing spi_device_csr_aliasing 21.550s 308.435us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_device_csr_mem_rw_with_rand_reset 4.000s 215.891us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_device_csr_rw 2.960s 101.554us 20 20 100.00
spi_device_csr_aliasing 21.550s 308.435us 5 5 100.00
V1 mem_walk spi_device_mem_walk 0.740s 12.202us 5 5 100.00
V1 mem_partial_access spi_device_mem_partial_access 1.910s 207.612us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 csb_read spi_device_csb_read 0.830s 64.637us 50 50 100.00
V2 mem_parity spi_device_mem_parity 1.180s 28.528us 20 20 100.00
V2 mem_cfg spi_device_ram_cfg 0.740s 73.259us 1 1 100.00
V2 tpm_read spi_device_tpm_rw 11.610s 381.035us 50 50 100.00
V2 tpm_write spi_device_tpm_rw 11.610s 381.035us 50 50 100.00
V2 tpm_hw_reg spi_device_tpm_read_hw_reg 21.490s 26.375ms 50 50 100.00
spi_device_tpm_sts_read 1.150s 141.986us 50 50 100.00
V2 tpm_fully_random_case spi_device_tpm_all 54.720s 10.294ms 50 50 100.00
V2 pass_cmd_filtering spi_device_pass_cmd_filtering 37.150s 12.697ms 50 50 100.00
spi_device_flash_all 8.569m 295.029ms 50 50 100.00
V2 pass_addr_translation spi_device_pass_addr_payload_swap 27.720s 8.969ms 50 50 100.00
spi_device_flash_all 8.569m 295.029ms 50 50 100.00
V2 pass_payload_translation spi_device_pass_addr_payload_swap 27.720s 8.969ms 50 50 100.00
spi_device_flash_all 8.569m 295.029ms 50 50 100.00
V2 cmd_info_slots spi_device_flash_all 8.569m 295.029ms 50 50 100.00
V2 cmd_read_status spi_device_intercept 28.570s 11.165ms 50 50 100.00
spi_device_flash_all 8.569m 295.029ms 50 50 100.00
V2 cmd_read_jedec spi_device_intercept 28.570s 11.165ms 50 50 100.00
spi_device_flash_all 8.569m 295.029ms 50 50 100.00
V2 cmd_read_sfdp spi_device_intercept 28.570s 11.165ms 50 50 100.00
spi_device_flash_all 8.569m 295.029ms 50 50 100.00
V2 cmd_fast_read spi_device_intercept 28.570s 11.165ms 50 50 100.00
spi_device_flash_all 8.569m 295.029ms 50 50 100.00
V2 cmd_read_pipeline spi_device_intercept 28.570s 11.165ms 50 50 100.00
spi_device_flash_all 8.569m 295.029ms 50 50 100.00
V2 flash_cmd_upload spi_device_upload 38.670s 23.248ms 50 50 100.00
V2 mailbox_command spi_device_mailbox 1.549m 68.876ms 50 50 100.00
V2 mailbox_cross_outside_command spi_device_mailbox 1.549m 68.876ms 50 50 100.00
V2 mailbox_cross_inside_command spi_device_mailbox 1.549m 68.876ms 50 50 100.00
V2 cmd_read_buffer spi_device_flash_mode 1.126m 17.726ms 50 50 100.00
spi_device_read_buffer_direct 17.240s 1.539ms 50 50 100.00
V2 cmd_dummy_cycle spi_device_mailbox 1.549m 68.876ms 50 50 100.00
spi_device_flash_all 8.569m 295.029ms 50 50 100.00
V2 quad_spi spi_device_flash_all 8.569m 295.029ms 50 50 100.00
V2 dual_spi spi_device_flash_all 8.569m 295.029ms 50 50 100.00
V2 4b_3b_feature spi_device_cfg_cmd 25.970s 2.537ms 50 50 100.00
V2 write_enable_disable spi_device_cfg_cmd 25.970s 2.537ms 50 50 100.00
V2 TPM_with_flash_or_passthrough_mode spi_device_flash_and_tpm 14.146m 229.428ms 50 50 100.00
V2 tpm_and_flash_trans_with_min_inactive_time spi_device_flash_and_tpm_min_idle 7.164m 43.543ms 50 50 100.00
V2 stress_all spi_device_stress_all 23.497m 306.623ms 50 50 100.00
V2 alert_test spi_device_alert_test 0.810s 40.762us 50 50 100.00
V2 intr_test spi_device_intr_test 0.870s 46.705us 50 50 100.00
V2 tl_d_oob_addr_access spi_device_tl_errors 5.820s 555.523us 20 20 100.00
V2 tl_d_illegal_access spi_device_tl_errors 5.820s 555.523us 20 20 100.00
V2 tl_d_outstanding_access spi_device_csr_hw_reset 1.390s 78.444us 5 5 100.00
spi_device_csr_rw 2.960s 101.554us 20 20 100.00
spi_device_csr_aliasing 21.550s 308.435us 5 5 100.00
spi_device_same_csr_outstanding 4.390s 68.265us 20 20 100.00
V2 tl_d_partial_access spi_device_csr_hw_reset 1.390s 78.444us 5 5 100.00
spi_device_csr_rw 2.960s 101.554us 20 20 100.00
spi_device_csr_aliasing 21.550s 308.435us 5 5 100.00
spi_device_same_csr_outstanding 4.390s 68.265us 20 20 100.00
V2 TOTAL 961 961 100.00
V2S tl_intg_err spi_device_sec_cm 1.130s 290.137us 5 5 100.00
spi_device_tl_intg_err 24.270s 3.341ms 20 20 100.00
V2S sec_cm_bus_integrity spi_device_tl_intg_err 24.270s 3.341ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset spi_device_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
Unmapped tests spi_device_flash_mode_ignore_cmds 8.137m 71.045ms 49 50 98.00
TOTAL 1150 1151 99.91

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 8 8 8 100.00
V2 22 22 22 100.00
V2S 2 2 2 100.00
V3 1 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
96.07 98.44 94.08 98.62 89.36 97.28 95.43 99.26

Failure Buckets

Past Results