SPI_DEVICE/2P Simulation Results

Sunday August 18 2024 23:02:23 UTC

GitHub Revision: f1535c5540

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29514139809134543525249635699831421949407409612590789671953066019961489233719

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	7.910m	48.286ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.410s	200.990us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.760s	239.209us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	28.390s	1.806ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	16.160s	640.145us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.990s	222.026us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.760s	239.209us	20	20	100.00
		spi_device_csr_aliasing	16.160s	640.145us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.700s	13.319us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.070s	216.079us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.840s	69.022us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.150s	32.979us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.710s	25.385us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	11.520s	662.288us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	11.520s	662.288us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	24.510s	7.748ms	50	50	100.00
		spi_device_tpm_sts_read	1.080s	316.172us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	47.290s	41.304ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	29.790s	36.433ms	50	50	100.00
		spi_device_flash_all	9.460m	452.114ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	35.980s	24.387ms	50	50	100.00
		spi_device_flash_all	9.460m	452.114ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	35.980s	24.387ms	50	50	100.00
		spi_device_flash_all	9.460m	452.114ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	9.460m	452.114ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	51.530s	4.701ms	50	50	100.00
		spi_device_flash_all	9.460m	452.114ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	51.530s	4.701ms	50	50	100.00
		spi_device_flash_all	9.460m	452.114ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	51.530s	4.701ms	50	50	100.00
		spi_device_flash_all	9.460m	452.114ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	51.530s	4.701ms	50	50	100.00
		spi_device_flash_all	9.460m	452.114ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	51.530s	4.701ms	50	50	100.00
		spi_device_flash_all	9.460m	452.114ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	33.260s	10.845ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.021m	52.561ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.021m	52.561ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.021m	52.561ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.085m	20.102ms	50	50	100.00
		spi_device_read_buffer_direct	21.830s	4.145ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.021m	52.561ms	50	50	100.00
		spi_device_flash_all	9.460m	452.114ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	9.460m	452.114ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	9.460m	452.114ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	29.400s	2.364ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	29.400s	2.364ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	7.910m	48.286ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	10.062m	56.918ms	50	50	100.00
V2	stress_all	spi_device_stress_all	20.659m	137.960ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.780s	66.238us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.830s	51.891us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.260s	255.640us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.260s	255.640us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.410s	200.990us	5	5	100.00
		spi_device_csr_rw	2.760s	239.209us	20	20	100.00
		spi_device_csr_aliasing	16.160s	640.145us	5	5	100.00
		spi_device_same_csr_outstanding	4.200s	162.393us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.410s	200.990us	5	5	100.00
		spi_device_csr_rw	2.760s	239.209us	20	20	100.00
		spi_device_csr_aliasing	16.160s	640.145us	5	5	100.00
		spi_device_same_csr_outstanding	4.200s	162.393us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.180s	378.285us	5	5	100.00
		spi_device_tl_intg_err	23.280s	11.375ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	23.280s	11.375ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	6.474m	104.199ms	50	50	100.00
		TOTAL			1151	1151	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	98.44	94.08	98.62	89.36	97.28	95.43	99.26

Past Results

• Latest
• 2024.08.18_08.45.47
• 2024.08.17_07.26.15
• 2024.08.16_08.44.50
• 2024.08.15_05.41.36
• 2024.08.14_08.45.51
• 2024.08.13_08.11.43
• 2024.08.12_08.40.55