SPI_DEVICE/2P Simulation Results

Monday August 19 2024 23:02:17 UTC

GitHub Revision: e45ccd274a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 28901767565311589526059483176077826609560752276120463932311122284088110669824

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	12.288m	81.862ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.230s	559.983us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.840s	580.435us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	37.220s	46.882ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	15.300s	2.508ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.980s	140.635us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.840s	580.435us	20	20	100.00
		spi_device_csr_aliasing	15.300s	2.508ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.710s	53.922us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.590s	27.059us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.840s	19.678us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.150s	141.558us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.740s	16.035us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	10.330s	740.958us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	10.330s	740.958us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	19.750s	7.527ms	50	50	100.00
		spi_device_tpm_sts_read	1.110s	78.753us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	49.260s	60.857ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	41.130s	60.191ms	50	50	100.00
		spi_device_flash_all	7.785m	266.303ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	23.580s	8.269ms	50	50	100.00
		spi_device_flash_all	7.785m	266.303ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	23.580s	8.269ms	50	50	100.00
		spi_device_flash_all	7.785m	266.303ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	7.785m	266.303ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	39.190s	4.102ms	50	50	100.00
		spi_device_flash_all	7.785m	266.303ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	39.190s	4.102ms	50	50	100.00
		spi_device_flash_all	7.785m	266.303ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	39.190s	4.102ms	50	50	100.00
		spi_device_flash_all	7.785m	266.303ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	39.190s	4.102ms	50	50	100.00
		spi_device_flash_all	7.785m	266.303ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	39.190s	4.102ms	50	50	100.00
		spi_device_flash_all	7.785m	266.303ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	32.360s	20.881ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.573m	36.438ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.573m	36.438ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.573m	36.438ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.898m	16.125ms	50	50	100.00
		spi_device_read_buffer_direct	23.790s	2.263ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.573m	36.438ms	50	50	100.00
		spi_device_flash_all	7.785m	266.303ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	7.785m	266.303ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	7.785m	266.303ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	24.170s	3.178ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	24.170s	3.178ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	12.288m	81.862ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	13.817m	714.321ms	50	50	100.00
V2	stress_all	spi_device_stress_all	20.139m	123.246ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.870s	12.937us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.840s	15.478us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	6.790s	4.363ms	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	6.790s	4.363ms	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.230s	559.983us	5	5	100.00
		spi_device_csr_rw	2.840s	580.435us	20	20	100.00
		spi_device_csr_aliasing	15.300s	2.508ms	5	5	100.00
		spi_device_same_csr_outstanding	4.630s	503.741us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.230s	559.983us	5	5	100.00
		spi_device_csr_rw	2.840s	580.435us	20	20	100.00
		spi_device_csr_aliasing	15.300s	2.508ms	5	5	100.00
		spi_device_same_csr_outstanding	4.630s	503.741us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.200s	234.849us	5	5	100.00
		spi_device_tl_intg_err	22.930s	1.745ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	22.930s	1.745ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	6.607m	114.566ms	50	50	100.00
		TOTAL			1151	1151	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	98.45	94.08	98.62	89.36	97.29	95.43	99.26

Past Results

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