SPI_DEVICE/2P Simulation Results

Wednesday August 21 2024 01:12:47 UTC

GitHub Revision: 34b8fc33e3

Branch: earlgrey_1_0_0_2024_08_20_RC0

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 77645589415139663032322841827996135987237190720163469870959218015679941996572

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	8.728m	50.063ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.710s	167.575us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.730s	210.082us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	42.510s	17.953ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	16.600s	656.842us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.830s	148.785us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.730s	210.082us	20	20	100.00
		spi_device_csr_aliasing	16.600s	656.842us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	1.060s	13.749us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	3.020s	58.025us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	1.210s	33.876us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.590s	33.708us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.790s	34.660us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	11.160s	1.043ms	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	11.160s	1.043ms	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	44.380s	35.606ms	50	50	100.00
		spi_device_tpm_sts_read	1.550s	261.406us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.028m	11.156ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	41.900s	47.970ms	50	50	100.00
		spi_device_flash_all	10.764m	159.226ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	56.500s	12.656ms	50	50	100.00
		spi_device_flash_all	10.764m	159.226ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	56.500s	12.656ms	50	50	100.00
		spi_device_flash_all	10.764m	159.226ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	10.764m	159.226ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	35.290s	15.615ms	50	50	100.00
		spi_device_flash_all	10.764m	159.226ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	35.290s	15.615ms	50	50	100.00
		spi_device_flash_all	10.764m	159.226ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	35.290s	15.615ms	50	50	100.00
		spi_device_flash_all	10.764m	159.226ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	35.290s	15.615ms	50	50	100.00
		spi_device_flash_all	10.764m	159.226ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	35.290s	15.615ms	50	50	100.00
		spi_device_flash_all	10.764m	159.226ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	1.008m	59.220ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.939m	75.267ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.939m	75.267ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.939m	75.267ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.498m	6.773ms	50	50	100.00
		spi_device_read_buffer_direct	18.880s	965.368us	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.939m	75.267ms	50	50	100.00
		spi_device_flash_all	10.764m	159.226ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	10.764m	159.226ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	10.764m	159.226ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	32.450s	7.154ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	32.450s	7.154ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	8.728m	50.063ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	13.198m	85.437ms	50	50	100.00
V2	stress_all	spi_device_stress_all	22.782m	303.477ms	50	50	100.00
V2	alert_test	spi_device_alert_test	1.130s	48.227us	50	50	100.00
V2	intr_test	spi_device_intr_test	1.150s	30.167us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	6.450s	295.244us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	6.450s	295.244us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.710s	167.575us	5	5	100.00
		spi_device_csr_rw	3.730s	210.082us	20	20	100.00
		spi_device_csr_aliasing	16.600s	656.842us	5	5	100.00
		spi_device_same_csr_outstanding	5.130s	201.180us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.710s	167.575us	5	5	100.00
		spi_device_csr_rw	3.730s	210.082us	20	20	100.00
		spi_device_csr_aliasing	16.600s	656.842us	5	5	100.00
		spi_device_same_csr_outstanding	5.130s	201.180us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.900s	138.667us	5	5	100.00
		spi_device_tl_intg_err	23.120s	3.261ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	23.120s	3.261ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	5.759m	266.487ms	50	50	100.00
		TOTAL			1151	1151	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	98.44	94.08	98.62	89.36	97.28	95.43	99.26

Past Results

• Latest
• 2024.08.20_08.05.30
• 2024.08.19_08.19.04
• 2024.08.18_08.45.47
• 2024.08.17_07.26.15
• 2024.08.16_08.44.50
• 2024.08.15_05.41.36
• 2024.08.14_08.45.51