SPI_DEVICE/2P Simulation Results

Thursday August 22 2024 22:02:20 UTC

GitHub Revision: 0825c81be0

Branch: os_regression_2024_08_22

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 102736032995262985039236458937944411119924968439319752111682827040046827694889

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	7.268m	125.560ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.150s	27.782us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.370s	1.529ms	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	28.300s	1.681ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	18.880s	3.603ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.150s	109.977us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.370s	1.529ms	20	20	100.00
		spi_device_csr_aliasing	18.880s	3.603ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.570s	12.721us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.770s	915.638us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.730s	41.578us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.980s	38.835us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.620s	32.261us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	11.120s	6.540ms	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	11.120s	6.540ms	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	25.700s	37.782ms	50	50	100.00
		spi_device_tpm_sts_read	0.960s	153.631us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	39.760s	15.222ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	38.840s	14.607ms	50	50	100.00
		spi_device_flash_all	7.779m	75.573ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	20.050s	7.543ms	50	50	100.00
		spi_device_flash_all	7.779m	75.573ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	20.050s	7.543ms	50	50	100.00
		spi_device_flash_all	7.779m	75.573ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	7.779m	75.573ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	27.780s	15.903ms	50	50	100.00
		spi_device_flash_all	7.779m	75.573ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	27.780s	15.903ms	50	50	100.00
		spi_device_flash_all	7.779m	75.573ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	27.780s	15.903ms	50	50	100.00
		spi_device_flash_all	7.779m	75.573ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	27.780s	15.903ms	50	50	100.00
		spi_device_flash_all	7.779m	75.573ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	27.780s	15.903ms	50	50	100.00
		spi_device_flash_all	7.779m	75.573ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	34.480s	48.850ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.510m	30.478ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.510m	30.478ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.510m	30.478ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.017m	4.998ms	50	50	100.00
		spi_device_read_buffer_direct	17.580s	1.515ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.510m	30.478ms	50	50	100.00
		spi_device_flash_all	7.779m	75.573ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	7.779m	75.573ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	7.779m	75.573ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	21.660s	4.433ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	21.660s	4.433ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	7.268m	125.560ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	10.752m	320.274ms	50	50	100.00
V2	stress_all	spi_device_stress_all	14.021m	197.923ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.650s	39.081us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.740s	56.067us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.790s	874.257us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.790s	874.257us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.150s	27.782us	5	5	100.00
		spi_device_csr_rw	2.370s	1.529ms	20	20	100.00
		spi_device_csr_aliasing	18.880s	3.603ms	5	5	100.00
		spi_device_same_csr_outstanding	3.760s	393.151us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.150s	27.782us	5	5	100.00
		spi_device_csr_rw	2.370s	1.529ms	20	20	100.00
		spi_device_csr_aliasing	18.880s	3.603ms	5	5	100.00
		spi_device_same_csr_outstanding	3.760s	393.151us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	0.930s	234.649us	5	5	100.00
		spi_device_tl_intg_err	20.140s	4.518ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	20.140s	4.518ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	7.968m	76.873ms	50	50	100.00
		TOTAL			1151	1151	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	98.44	94.10	98.62	89.36	97.28	95.43	99.26

Past Results

• Latest
• 2024.08.22_14.22.37
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• 2024.08.19_08.19.04
• 2024.08.18_08.45.47
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