SPI_DEVICE/2P Simulation Results

Saturday August 24 2024 20:58:08 UTC

GitHub Revision: e733a8ef8a

Branch: os_regression_2024_08_24

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 36240513409906943553650221581975102764006655953510936167454320581301243659163

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	15.393m	62.441ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.200s	91.333us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.970s	112.044us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	48.460s	8.710ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	31.130s	3.032ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	5.530s	326.237us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.970s	112.044us	20	20	100.00
		spi_device_csr_aliasing	31.130s	3.032ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	1.060s	20.164us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	3.570s	132.659us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	1.250s	23.682us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.710s	33.496us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	1.160s	15.261us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	14.060s	199.301us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	14.060s	199.301us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	49.670s	9.513ms	50	50	100.00
		spi_device_tpm_sts_read	1.680s	450.263us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.274m	8.638ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	1.101m	13.636ms	50	50	100.00
		spi_device_flash_all	11.429m	236.937ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	42.600s	6.191ms	50	50	100.00
		spi_device_flash_all	11.429m	236.937ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	42.600s	6.191ms	50	50	100.00
		spi_device_flash_all	11.429m	236.937ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	11.429m	236.937ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	39.620s	13.850ms	50	50	100.00
		spi_device_flash_all	11.429m	236.937ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	39.620s	13.850ms	50	50	100.00
		spi_device_flash_all	11.429m	236.937ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	39.620s	13.850ms	50	50	100.00
		spi_device_flash_all	11.429m	236.937ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	39.620s	13.850ms	50	50	100.00
		spi_device_flash_all	11.429m	236.937ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	39.620s	13.850ms	50	50	100.00
		spi_device_flash_all	11.429m	236.937ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	1.127m	12.012ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	4.230m	227.966ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	4.230m	227.966ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	4.230m	227.966ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.565m	18.803ms	50	50	100.00
		spi_device_read_buffer_direct	31.230s	1.740ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	4.230m	227.966ms	50	50	100.00
		spi_device_flash_all	11.429m	236.937ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	11.429m	236.937ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	11.429m	236.937ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	41.700s	3.145ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	41.700s	3.145ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	15.393m	62.441ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	17.406m	325.933ms	50	50	100.00
V2	stress_all	spi_device_stress_all	33.273m	145.302ms	50	50	100.00
V2	alert_test	spi_device_alert_test	1.150s	15.663us	50	50	100.00
V2	intr_test	spi_device_intr_test	1.200s	30.453us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	8.420s	1.157ms	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	8.420s	1.157ms	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.200s	91.333us	5	5	100.00
		spi_device_csr_rw	3.970s	112.044us	20	20	100.00
		spi_device_csr_aliasing	31.130s	3.032ms	5	5	100.00
		spi_device_same_csr_outstanding	6.140s	378.531us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.200s	91.333us	5	5	100.00
		spi_device_csr_rw	3.970s	112.044us	20	20	100.00
		spi_device_csr_aliasing	31.130s	3.032ms	5	5	100.00
		spi_device_same_csr_outstanding	6.140s	378.531us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	2.050s	561.288us	5	5	100.00
		spi_device_tl_intg_err	30.320s	840.992us	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	30.320s	840.992us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	12.617m	66.462ms	50	50	100.00
		TOTAL			1151	1151	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	98.44	94.11	98.62	89.36	97.28	95.43	99.26

Past Results

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