SPI_DEVICE/2P Simulation Results

Monday August 26 2024 23:33:20 UTC

GitHub Revision: 4674f625b3

Branch: os_regression_2024_08_26

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 27137705585251537962012108482438895412147493342955425380690984800523869492310

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	12.011m	69.300ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.950s	41.051us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.800s	207.587us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	34.760s	554.634us	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	26.980s	2.575ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.750s	159.336us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.800s	207.587us	20	20	100.00
		spi_device_csr_aliasing	26.980s	2.575ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	1.040s	12.569us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	3.010s	360.177us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	1.230s	80.668us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.590s	123.714us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	1.080s	18.058us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	10.300s	169.281us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	10.300s	169.281us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	42.660s	10.753ms	50	50	100.00
		spi_device_tpm_sts_read	1.630s	98.706us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.085m	36.388ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	42.080s	47.065ms	50	50	100.00
		spi_device_flash_all	9.615m	294.891ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	1.582m	72.231ms	50	50	100.00
		spi_device_flash_all	9.615m	294.891ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	1.582m	72.231ms	50	50	100.00
		spi_device_flash_all	9.615m	294.891ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	9.615m	294.891ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	28.890s	2.982ms	50	50	100.00
		spi_device_flash_all	9.615m	294.891ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	28.890s	2.982ms	50	50	100.00
		spi_device_flash_all	9.615m	294.891ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	28.890s	2.982ms	50	50	100.00
		spi_device_flash_all	9.615m	294.891ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	28.890s	2.982ms	50	50	100.00
		spi_device_flash_all	9.615m	294.891ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	28.890s	2.982ms	50	50	100.00
		spi_device_flash_all	9.615m	294.891ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	52.810s	12.155ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.751m	25.768ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.751m	25.768ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.751m	25.768ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	45.350s	14.875ms	50	50	100.00
		spi_device_read_buffer_direct	22.060s	5.647ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.751m	25.768ms	50	50	100.00
		spi_device_flash_all	9.615m	294.891ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	9.615m	294.891ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	9.615m	294.891ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	31.580s	2.229ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	31.580s	2.229ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	12.011m	69.300ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	14.351m	138.477ms	50	50	100.00
V2	stress_all	spi_device_stress_all	17.419m	468.989ms	50	50	100.00
V2	alert_test	spi_device_alert_test	1.140s	13.839us	50	50	100.00
V2	intr_test	spi_device_intr_test	1.140s	31.737us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	7.340s	895.367us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	7.340s	895.367us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.950s	41.051us	5	5	100.00
		spi_device_csr_rw	3.800s	207.587us	20	20	100.00
		spi_device_csr_aliasing	26.980s	2.575ms	5	5	100.00
		spi_device_same_csr_outstanding	5.710s	430.708us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.950s	41.051us	5	5	100.00
		spi_device_csr_rw	3.800s	207.587us	20	20	100.00
		spi_device_csr_aliasing	26.980s	2.575ms	5	5	100.00
		spi_device_same_csr_outstanding	5.710s	430.708us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.680s	55.256us	5	5	100.00
		spi_device_tl_intg_err	21.090s	4.273ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	21.090s	4.273ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	7.341m	52.117ms	49	50	98.00
		TOTAL			1150	1151	99.91

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.06	98.44	94.08	98.62	89.36	97.28	95.43	99.21

Failure Buckets

• UVM_ERROR (spi_device_pass_base_vseq.sv:704) [spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be * has 1 failures:
  • Test spi_device_flash_mode_ignore_cmds has 1 failures.

    • 7.spi_device_flash_mode_ignore_cmds.58414594705244337404426813965598452403179906317932033135497552650286287834889
      Line 76, in log /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/7.spi_device_flash_mode_ignore_cmds/latest/run.log

        UVM_ERROR @ 940468267 ps: (spi_device_pass_base_vseq.sv:704) [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
        tl_ul_fuzzy_flash_status_q[i] = 0x7353b4
        UVM_INFO @ 1137932919 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 3/4
        UVM_INFO @ 1150360240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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