SPI_DEVICE/2P Simulation Results

Wednesday August 28 2024 16:26:26 UTC

GitHub Revision: a861deb3de

Branch: os_regression_2024_08_28

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1071354200461384473511155521960728188378582408849032283874664554749864050652

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	9.172m	44.849ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.030s	196.473us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.800s	391.349us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	49.130s	7.211ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	31.460s	3.606ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	5.170s	994.068us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.800s	391.349us	20	20	100.00
		spi_device_csr_aliasing	31.460s	3.606ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	1.060s	10.430us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.960s	63.027us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	1.240s	21.810us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.630s	31.878us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	1.100s	25.477us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	15.630s	1.191ms	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	15.630s	1.191ms	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	53.930s	10.479ms	50	50	100.00
		spi_device_tpm_sts_read	1.520s	291.907us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.215m	33.916ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	55.660s	24.547ms	50	50	100.00
		spi_device_flash_all	13.434m	367.786ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	58.390s	40.143ms	50	50	100.00
		spi_device_flash_all	13.434m	367.786ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	58.390s	40.143ms	50	50	100.00
		spi_device_flash_all	13.434m	367.786ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	13.434m	367.786ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	36.490s	5.969ms	50	50	100.00
		spi_device_flash_all	13.434m	367.786ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	36.490s	5.969ms	50	50	100.00
		spi_device_flash_all	13.434m	367.786ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	36.490s	5.969ms	50	50	100.00
		spi_device_flash_all	13.434m	367.786ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	36.490s	5.969ms	50	50	100.00
		spi_device_flash_all	13.434m	367.786ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	36.490s	5.969ms	50	50	100.00
		spi_device_flash_all	13.434m	367.786ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	44.840s	25.628ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	3.420m	16.721ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	3.420m	16.721ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	3.420m	16.721ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	49.530s	12.075ms	50	50	100.00
		spi_device_read_buffer_direct	26.410s	4.091ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	3.420m	16.721ms	50	50	100.00
		spi_device_flash_all	13.434m	367.786ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	13.434m	367.786ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	13.434m	367.786ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	34.020s	2.371ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	34.020s	2.371ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	9.172m	44.849ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	13.026m	72.836ms	50	50	100.00
V2	stress_all	spi_device_stress_all	14.457m	79.483ms	50	50	100.00
V2	alert_test	spi_device_alert_test	1.140s	18.172us	50	50	100.00
V2	intr_test	spi_device_intr_test	1.170s	60.209us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	6.740s	395.541us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	6.740s	395.541us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.030s	196.473us	5	5	100.00
		spi_device_csr_rw	3.800s	391.349us	20	20	100.00
		spi_device_csr_aliasing	31.460s	3.606ms	5	5	100.00
		spi_device_same_csr_outstanding	6.000s	873.898us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.030s	196.473us	5	5	100.00
		spi_device_csr_rw	3.800s	391.349us	20	20	100.00
		spi_device_csr_aliasing	31.460s	3.606ms	5	5	100.00
		spi_device_same_csr_outstanding	6.000s	873.898us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.840s	168.051us	5	5	100.00
		spi_device_tl_intg_err	29.960s	3.904ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	29.960s	3.904ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	13.259m	162.035ms	50	50	100.00
		TOTAL			1151	1151	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	98.44	94.08	98.62	89.36	97.29	95.43	99.26

Past Results

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