SPI_DEVICE/2P Simulation Results

Sunday September 01 2024 02:56:32 UTC

GitHub Revision: ed1c41cd0f

Branch: os_regression_2024_08_31

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 79046303479535931055412478968949166876277637335647713094117953182855865639399

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	13.203m	56.076ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.170s	187.707us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.840s	93.917us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	49.010s	10.817ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	32.330s	5.397ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	5.460s	651.065us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.840s	93.917us	20	20	100.00
		spi_device_csr_aliasing	32.330s	5.397ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	1.040s	10.474us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.970s	238.344us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	1.250s	16.925us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.650s	34.942us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.790s	25.661us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	10.260s	709.738us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	10.260s	709.738us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	58.750s	10.471ms	50	50	100.00
		spi_device_tpm_sts_read	1.660s	111.059us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	46.310s	3.439ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	46.600s	9.102ms	50	50	100.00
		spi_device_flash_all	18.260m	1.335s	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	1.458m	31.800ms	50	50	100.00
		spi_device_flash_all	18.260m	1.335s	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	1.458m	31.800ms	50	50	100.00
		spi_device_flash_all	18.260m	1.335s	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	18.260m	1.335s	50	50	100.00
V2	cmd_read_status	spi_device_intercept	29.910s	13.031ms	50	50	100.00
		spi_device_flash_all	18.260m	1.335s	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	29.910s	13.031ms	50	50	100.00
		spi_device_flash_all	18.260m	1.335s	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	29.910s	13.031ms	50	50	100.00
		spi_device_flash_all	18.260m	1.335s	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	29.910s	13.031ms	50	50	100.00
		spi_device_flash_all	18.260m	1.335s	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	29.910s	13.031ms	50	50	100.00
		spi_device_flash_all	18.260m	1.335s	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	48.440s	9.518ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.420m	88.179ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.420m	88.179ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.420m	88.179ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.350m	10.695ms	50	50	100.00
		spi_device_read_buffer_direct	28.410s	11.294ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.420m	88.179ms	50	50	100.00
		spi_device_flash_all	18.260m	1.335s	50	50	100.00
V2	quad_spi	spi_device_flash_all	18.260m	1.335s	50	50	100.00
V2	dual_spi	spi_device_flash_all	18.260m	1.335s	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	33.750s	4.597ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	33.750s	4.597ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	13.203m	56.076ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	14.909m	396.598ms	50	50	100.00
V2	stress_all	spi_device_stress_all	12.428m	63.573ms	50	50	100.00
V2	alert_test	spi_device_alert_test	1.180s	20.595us	50	50	100.00
V2	intr_test	spi_device_intr_test	1.180s	17.601us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	7.130s	196.274us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	7.130s	196.274us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.170s	187.707us	5	5	100.00
		spi_device_csr_rw	3.840s	93.917us	20	20	100.00
		spi_device_csr_aliasing	32.330s	5.397ms	5	5	100.00
		spi_device_same_csr_outstanding	5.900s	261.157us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.170s	187.707us	5	5	100.00
		spi_device_csr_rw	3.840s	93.917us	20	20	100.00
		spi_device_csr_aliasing	32.330s	5.397ms	5	5	100.00
		spi_device_same_csr_outstanding	5.900s	261.157us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.740s	819.778us	5	5	100.00
		spi_device_tl_intg_err	28.120s	1.031ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	28.120s	1.031ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	12.003m	281.077ms	50	50	100.00
		TOTAL			1151	1151	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	98.44	94.08	98.62	89.36	97.28	95.43	99.26

Past Results

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