SPI_DEVICE/2P Simulation Results

Tuesday September 03 2024 20:34:49 UTC

GitHub Revision: 372a6306e0

Branch: os_regression_2024_09_03

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 13282233770562214583722256565474794620746865855733889385758507057043002787586

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	7.938m	128.181ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.290s	129.871us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.820s	448.701us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	29.330s	527.970us	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	18.320s	293.704us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.590s	243.834us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.820s	448.701us	20	20	100.00
		spi_device_csr_aliasing	18.320s	293.704us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.830s	121.358us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.720s	47.031us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	1.250s	20.775us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.580s	44.384us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	1.120s	42.055us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	8.350s	1.833ms	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	8.350s	1.833ms	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	34.540s	15.684ms	50	50	100.00
		spi_device_tpm_sts_read	1.950s	224.654us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	51.080s	31.122ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	39.750s	45.145ms	50	50	100.00
		spi_device_flash_all	6.268m	48.814ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	38.810s	104.431ms	50	50	100.00
		spi_device_flash_all	6.268m	48.814ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	38.810s	104.431ms	50	50	100.00
		spi_device_flash_all	6.268m	48.814ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	6.268m	48.814ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	45.350s	21.067ms	50	50	100.00
		spi_device_flash_all	6.268m	48.814ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	45.350s	21.067ms	50	50	100.00
		spi_device_flash_all	6.268m	48.814ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	45.350s	21.067ms	50	50	100.00
		spi_device_flash_all	6.268m	48.814ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	45.350s	21.067ms	50	50	100.00
		spi_device_flash_all	6.268m	48.814ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	45.350s	21.067ms	50	50	100.00
		spi_device_flash_all	6.268m	48.814ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	1.262m	64.162ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.759m	18.788ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.759m	18.788ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.759m	18.788ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.795m	9.614ms	50	50	100.00
		spi_device_read_buffer_direct	21.320s	1.770ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.759m	18.788ms	50	50	100.00
		spi_device_flash_all	6.268m	48.814ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	6.268m	48.814ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	6.268m	48.814ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	28.240s	4.110ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	28.240s	4.110ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	7.938m	128.181ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	12.558m	170.937ms	50	50	100.00
V2	stress_all	spi_device_stress_all	17.643m	257.556ms	50	50	100.00
V2	alert_test	spi_device_alert_test	1.140s	46.035us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.990s	170.158us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.850s	84.636us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.850s	84.636us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.290s	129.871us	5	5	100.00
		spi_device_csr_rw	2.820s	448.701us	20	20	100.00
		spi_device_csr_aliasing	18.320s	293.704us	5	5	100.00
		spi_device_same_csr_outstanding	4.430s	229.008us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.290s	129.871us	5	5	100.00
		spi_device_csr_rw	2.820s	448.701us	20	20	100.00
		spi_device_csr_aliasing	18.320s	293.704us	5	5	100.00
		spi_device_same_csr_outstanding	4.430s	229.008us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.990s	124.493us	5	5	100.00
		spi_device_tl_intg_err	21.640s	4.575ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	21.640s	4.575ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	5.982m	52.425ms	49	50	98.00
		TOTAL			1150	1151	99.91

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	98.44	94.08	98.62	89.36	97.28	95.43	99.26

Failure Buckets

• Job timed out after * minutes has 1 failures:
  • Test spi_device_flash_mode_ignore_cmds has 1 failures.

    • 4.spi_device_flash_mode_ignore_cmds.59424713253637306128066267350957692034517685932162611016986702321202221906036
      Log /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/4.spi_device_flash_mode_ignore_cmds/latest/run.log

        Job timed out after 60 minutes
      

Past Results

• Latest
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• 2024.08.29_23.16.03
• 2024.08.28_06.59.33
• 2024.08.26_02.21.05
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• 2024.08.22_14.22.37
• 2024.08.20_08.05.30