SPI_DEVICE/2P Simulation Results

Monday September 09 2024 02:20:26 UTC

GitHub Revision: af2d1709f9

Branch: os_regression_2024_09_08

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 13980492992314588037778262839223440914483141513139750793389284041724730149540

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	8.408m	351.032ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.120s	211.960us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.720s	467.028us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	42.930s	2.770ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	23.830s	4.051ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.820s	169.503us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.720s	467.028us	20	20	100.00
		spi_device_csr_aliasing	23.830s	4.051ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	1.020s	15.181us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	3.040s	130.823us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	1.260s	24.374us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.590s	36.043us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.660s	15.834us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	7.580s	217.741us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	7.580s	217.741us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	29.320s	17.392ms	50	50	100.00
		spi_device_tpm_sts_read	1.670s	435.878us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.105m	9.464ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	36.250s	6.244ms	50	50	100.00
		spi_device_flash_all	10.868m	82.466ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	51.600s	14.062ms	50	50	100.00
		spi_device_flash_all	10.868m	82.466ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	51.600s	14.062ms	50	50	100.00
		spi_device_flash_all	10.868m	82.466ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	10.868m	82.466ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	33.390s	8.215ms	50	50	100.00
		spi_device_flash_all	10.868m	82.466ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	33.390s	8.215ms	50	50	100.00
		spi_device_flash_all	10.868m	82.466ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	33.390s	8.215ms	50	50	100.00
		spi_device_flash_all	10.868m	82.466ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	33.390s	8.215ms	50	50	100.00
		spi_device_flash_all	10.868m	82.466ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	33.390s	8.215ms	50	50	100.00
		spi_device_flash_all	10.868m	82.466ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	33.920s	15.899ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	3.373m	39.573ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	3.373m	39.573ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	3.373m	39.573ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.297m	5.401ms	50	50	100.00
		spi_device_read_buffer_direct	19.310s	1.843ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	3.373m	39.573ms	50	50	100.00
		spi_device_flash_all	10.868m	82.466ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	10.868m	82.466ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	10.868m	82.466ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	28.370s	1.951ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	28.370s	1.951ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	8.408m	351.032ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	9.482m	109.187ms	50	50	100.00
V2	stress_all	spi_device_stress_all	15.903m	91.505ms	50	50	100.00
V2	alert_test	spi_device_alert_test	1.140s	73.666us	50	50	100.00
V2	intr_test	spi_device_intr_test	1.180s	27.700us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	7.330s	826.049us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	7.330s	826.049us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.120s	211.960us	5	5	100.00
		spi_device_csr_rw	3.720s	467.028us	20	20	100.00
		spi_device_csr_aliasing	23.830s	4.051ms	5	5	100.00
		spi_device_same_csr_outstanding	5.960s	207.460us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.120s	211.960us	5	5	100.00
		spi_device_csr_rw	3.720s	467.028us	20	20	100.00
		spi_device_csr_aliasing	23.830s	4.051ms	5	5	100.00
		spi_device_same_csr_outstanding	5.960s	207.460us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.670s	935.788us	5	5	100.00
		spi_device_tl_intg_err	24.960s	1.087ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	24.960s	1.087ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	6.423m	171.707ms	50	50	100.00
		TOTAL			1151	1151	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	98.44	94.08	98.62	89.36	97.28	95.43	99.26

Past Results

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