SPI_HOST Simulation Results

Friday May 26 2023 07:06:59 UTC

GitHub Revision: `213e792ea`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 2340441291

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	10.083m	52.899ms	49	50	98.00
V1	csr_hw_reset	spi_host_csr_hw_reset	3.000s	18.393us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	3.000s	56.239us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	234.317us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	3.000s	38.054us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	63.202us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	3.000s	56.239us	20	20	100.00
		spi_host_csr_aliasing	3.000s	38.054us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	3.000s	21.578us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	3.000s	20.553us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	performance	spi_host_performance	4.000s	30.081us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	3.183m	17.921ms	50	50	100.00
		spi_host_error_cmd	4.000s	57.299us	50	50	100.00
		spi_host_event	26.017m	75.275ms	50	50	100.00
V2	clock_rate	spi_host_speed	6.100m	7.576ms	50	50	100.00
V2	speed	spi_host_speed	6.100m	7.576ms	50	50	100.00
V2	chip_select_timing	spi_host_speed	6.100m	7.576ms	50	50	100.00
V2	sw_reset	spi_host_sw_reset	4.100m	11.211ms	44	50	88.00
V2	passthrough_mode	spi_host_passthrough_mode	4.000s	182.316us	50	50	100.00
V2	cpol_cpha	spi_host_speed	6.100m	7.576ms	50	50	100.00
V2	full_cycle	spi_host_speed	6.100m	7.576ms	50	50	100.00
V2	duplex	spi_host_smoke	10.083m	52.899ms	49	50	98.00
V2	tx_rx_only	spi_host_smoke	10.083m	52.899ms	49	50	98.00
V2	stress_all	spi_host_stress_all	4.017m	10.939ms	48	50	96.00
V2	spien	spi_host_spien	5.783m	29.113ms	50	50	100.00
V2	stall	spi_host_status_stall	11.667m	65.862ms	50	50	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	1.350m	7.181ms	49	50	98.00
V2	alert_test	spi_host_alert_test	4.000s	16.517us	50	50	100.00
V2	intr_test	spi_host_intr_test	4.000s	23.218us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	6.000s	193.773us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	6.000s	193.773us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	3.000s	18.393us	5	5	100.00
		spi_host_csr_rw	3.000s	56.239us	20	20	100.00
		spi_host_csr_aliasing	3.000s	38.054us	5	5	100.00
		spi_host_same_csr_outstanding	4.000s	31.765us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	3.000s	18.393us	5	5	100.00
		spi_host_csr_rw	3.000s	56.239us	20	20	100.00
		spi_host_csr_aliasing	3.000s	38.054us	5	5	100.00
		spi_host_same_csr_outstanding	4.000s	31.765us	20	20	100.00
V2		TOTAL			681	690	98.70
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	53.641us	20	20	100.00
		spi_host_sec_cm	3.000s	113.050us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	53.641us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	winbond	winbond			0	0	--
V3	stress_all_with_rand_reset	spi_host_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			820	830	98.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	15	15	12	80.00
V2S	2	2	2	100.00
V3	2	0	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.08	98.19	95.98	99.74	96.25	95.70	100.00	98.60	91.29

Failure Buckets

UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 5 failures:

Test spi_host_sw_reset has 4 failures.

1.spi_host_sw_reset.2590649399
Line 287, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_sw_reset/latest/run.log

  UVM_FATAL @ 12469807068 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xbb1e7f94) == 0x0
  UVM_INFO @ 12469807068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.spi_host_sw_reset.144727120
Line 269, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_sw_reset/latest/run.log

  UVM_FATAL @ 10668958304 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x52a18fd4) == 0x0
  UVM_INFO @ 10668958304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test spi_host_stress_all has 1 failures.

40.spi_host_stress_all.3362597047
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/40.spi_host_stress_all/latest/run.log

  UVM_FATAL @ 10938793187 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x2df7b7d4) == 0x0
  UVM_INFO @ 10938793187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 3 failures:

Test spi_host_stress_all has 1 failures.

7.spi_host_stress_all.3209885540
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_stress_all/latest/run.log

  UVM_FATAL @ 19804133407 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x373b4c94) == 0x0
  UVM_INFO @ 19804133407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test spi_host_smoke has 1 failures.

26.spi_host_smoke.4064703822
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/26.spi_host_smoke/latest/run.log

  UVM_FATAL @ 121202270476 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x32225ed4) == 0x0
  UVM_INFO @ 121202270476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test spi_host_idlecsbactive has 1 failures.

42.spi_host_idlecsbactive.2141162516
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/42.spi_host_idlecsbactive/latest/run.log

  UVM_FATAL @ 10099341914 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x76d13d54) == 0x0
  UVM_INFO @ 10099341914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 2 failures:

Test spi_host_sw_reset has 2 failures.

19.spi_host_sw_reset.3650735646
Line 287, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/19.spi_host_sw_reset/latest/run.log

  UVM_FATAL @ 11048607951 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xd34f27d4) == 0x0
  UVM_INFO @ 11048607951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

25.spi_host_sw_reset.3556666351
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/25.spi_host_sw_reset/latest/run.log

  UVM_FATAL @ 10002618315 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xd7b3ca14) == 0x0
  UVM_INFO @ 10002618315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---