SPI_HOST Simulation Results

Sunday February 25 2024 20:02:21 UTC

GitHub Revision: `49a27e136c`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 17821327886248910358472250431024817182401150698618588470408418907520000067582

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	10.150m	22.123ms	46	50	92.00
V1	csr_hw_reset	spi_host_csr_hw_reset	3.000s	19.884us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	9.000s	28.976us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	4.000s	634.119us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	15.000s	59.391us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	14.000s	31.546us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	9.000s	28.976us	20	20	100.00
		spi_host_csr_aliasing	15.000s	59.391us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	2.000s	21.887us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	7.000s	183.893us	5	5	100.00
V1		TOTAL			111	115	96.52
V2	performance	spi_host_performance	3.000s	131.794us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	3.617m	16.908ms	50	50	100.00
		spi_host_error_cmd	3.000s	18.264us	50	50	100.00
		spi_host_event	28.300m	37.932ms	50	50	100.00
V2	clock_rate	spi_host_speed	6.133m	7.619ms	50	50	100.00
V2	speed	spi_host_speed	6.133m	7.619ms	50	50	100.00
V2	chip_select_timing	spi_host_speed	6.133m	7.619ms	50	50	100.00
V2	sw_reset	spi_host_sw_reset	4.517m	10.195ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	3.000s	1.989ms	50	50	100.00
V2	cpol_cpha	spi_host_speed	6.133m	7.619ms	50	50	100.00
V2	full_cycle	spi_host_speed	6.133m	7.619ms	50	50	100.00
V2	duplex	spi_host_smoke	10.150m	22.123ms	46	50	92.00
V2	tx_rx_only	spi_host_smoke	10.150m	22.123ms	46	50	92.00
V2	stress_all	spi_host_stress_all	5.200m	13.447ms	45	50	90.00
V2	spien	spi_host_spien	5.983m	28.745ms	49	50	98.00
V2	stall	spi_host_status_stall	9.400m	12.569ms	46	50	92.00
V2	Idlecsbactive	spi_host_idlecsbactive	47.000s	7.359ms	50	50	100.00
V2	alert_test	spi_host_alert_test	3.000s	42.302us	50	50	100.00
V2	intr_test	spi_host_intr_test	13.000s	16.777us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	8.000s	60.916us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	8.000s	60.916us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	3.000s	19.884us	5	5	100.00
		spi_host_csr_rw	9.000s	28.976us	20	20	100.00
		spi_host_csr_aliasing	15.000s	59.391us	5	5	100.00
		spi_host_same_csr_outstanding	13.000s	21.910us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	3.000s	19.884us	5	5	100.00
		spi_host_csr_rw	9.000s	28.976us	20	20	100.00
		spi_host_csr_aliasing	15.000s	59.391us	5	5	100.00
		spi_host_same_csr_outstanding	13.000s	21.910us	20	20	100.00
V2		TOTAL			680	690	98.55
V2S	tl_intg_err	spi_host_tl_intg_err	10.000s	74.575us	20	20	100.00
		spi_host_sec_cm	2.000s	111.293us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	10.000s	74.575us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	winbond	winbond			0	0	--
V3	stress_all_with_rand_reset	spi_host_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			816	830	98.31

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	15	15	12	80.00
V2S	2	2	2	100.00
V3	2	0	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.07	98.13	95.98	99.73	96.61	95.70	100.00	98.60	90.87

Failure Buckets

UVM_FATAL (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 6 failures:

Test spi_host_smoke has 2 failures.

8.spi_host_smoke.61032425738036657425955276233154569182583971604047572282625342435088903639922
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_smoke/latest/run.log

  UVM_FATAL @ 122402025858 ps: (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xe5ea8fd4) == 0x0
  UVM_INFO @ 122402025858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

27.spi_host_smoke.110130839425064594276232642108724826174872379473904553920117419038911007237213
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/27.spi_host_smoke/latest/run.log

  UVM_FATAL @ 150426011792 ps: (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xb84cbf94) == 0x0
  UVM_INFO @ 150426011792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test spi_host_status_stall has 2 failures.

9.spi_host_status_stall.27913360589538732007123376322845055931832107567993127590652296733427597987694
Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_status_stall/latest/run.log

  UVM_FATAL @ 117047412634 ps: (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xe62c6154) == 0x0
  UVM_INFO @ 117047412634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

15.spi_host_status_stall.15825636245505696602067014697285932786576368432205937954883604069924053516491
Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/15.spi_host_status_stall/latest/run.log

  UVM_FATAL @ 147522486977 ps: (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x9f91c4d4) == 0x0
  UVM_INFO @ 147522486977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test spi_host_stress_all has 2 failures.

15.spi_host_stress_all.26193380295896121086461901148294324692579662992473922414807237581388996472606
Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/15.spi_host_stress_all/latest/run.log

  UVM_FATAL @ 28734493354 ps: (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x41ae8614) == 0x0
  UVM_INFO @ 28734493354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

33.spi_host_stress_all.45214288927756400866841961409147184792948964422540870309114344442834886171173
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/33.spi_host_stress_all/latest/run.log

  UVM_FATAL @ 16474548256 ps: (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x16bcdf94) == 0x0
  UVM_INFO @ 16474548256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 3 failures:
- Test spi_host_smoke has 1 failures.
  - 16.spi_host_smoke.47675545713271820615837585717282865201785128440347606499472698826297037980016
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/16.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 177092139878 ps: (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xf9c9f6d4) == 0x0
  UVM_INFO @ 177092139878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_stress_all has 1 failures.
  - 35.spi_host_stress_all.46438383228704681361726549907653062895725638262134064414426355844525073495010
    Line 280, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/35.spi_host_stress_all/latest/run.log
```
  UVM_FATAL @ 16118299164 ps: (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x65c66054) == 0x0
  UVM_INFO @ 16118299164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_status_stall has 1 failures.
  - 49.spi_host_status_stall.104083028952106178344818864713898290072464159478192904426050509284338183228267
    Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/49.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 117917299770 ps: (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x58c2c654) == 0x0
  UVM_INFO @ 117917299770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 2 failures:
- Test spi_host_stress_all has 2 failures.
  - 5.spi_host_stress_all.30653958561766969474404693518344815864094185835905063378603995203816276153763
    Line 318, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_stress_all/latest/run.log
```
  UVM_FATAL @ 13446748064 ps: (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x42901694) == 0x0
  UVM_INFO @ 13446748064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 25.spi_host_stress_all.91640853407896504305119585145050160787975154586863917043699802560944904268330
    Line 316, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/25.spi_host_stress_all/latest/run.log
```
  UVM_FATAL @ 11526402376 ps: (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xbaae7114) == 0x0
  UVM_INFO @ 11526402376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 1 failures:
- Test spi_host_status_stall has 1 failures.
  - 29.spi_host_status_stall.89265271584142299396254268700529372032553685412562448502045619553661199350316
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/29.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 17965232401 ps: (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x2704dfd4) == 0x1
  UVM_INFO @ 17965232401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 1 failures:
- Test spi_host_smoke has 1 failures.
  - 38.spi_host_smoke.48816268030926517679759602082319322426236266819879949017183539170389154667406
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/38.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 10019491475 ps: (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x319d3714) == 0x0
  UVM_INFO @ 10019491475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 1 failures:
- Test spi_host_spien has 1 failures.
  - 39.spi_host_spien.98201215071036933096602730173766846132733476872179225713788548562920519194440
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/39.spi_host_spien/latest/run.log
```
  UVM_FATAL @ 28068123203 ps: (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x987aef54) == 0x1
  UVM_INFO @ 28068123203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```