SPI_HOST Simulation Results

Thursday February 29 2024 20:02:24 UTC

GitHub Revision: `e0c4026501`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 37435771356197831901593787335841447308974032110687249165442170486932885997295

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	10.283m	15.400ms	49	50	98.00
V1	csr_hw_reset	spi_host_csr_hw_reset	3.000s	18.385us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	4.000s	22.617us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	1.032ms	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	3.000s	80.036us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	56.208us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	4.000s	22.617us	20	20	100.00
		spi_host_csr_aliasing	3.000s	80.036us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	4.000s	38.678us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	3.000s	19.802us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	performance	spi_host_performance	6.000s	98.545us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	2.500m	39.731ms	48	50	96.00
		spi_host_error_cmd	7.000s	22.107us	50	50	100.00
		spi_host_event	22.367m	139.190ms	50	50	100.00
V2	clock_rate	spi_host_speed	6.200m	8.694ms	50	50	100.00
V2	speed	spi_host_speed	6.200m	8.694ms	50	50	100.00
V2	chip_select_timing	spi_host_speed	6.200m	8.694ms	50	50	100.00
V2	sw_reset	spi_host_sw_reset	9.183m	29.529ms	49	50	98.00
V2	passthrough_mode	spi_host_passthrough_mode	8.000s	2.816ms	50	50	100.00
V2	cpol_cpha	spi_host_speed	6.200m	8.694ms	50	50	100.00
V2	full_cycle	spi_host_speed	6.200m	8.694ms	50	50	100.00
V2	duplex	spi_host_smoke	10.283m	15.400ms	49	50	98.00
V2	tx_rx_only	spi_host_smoke	10.283m	15.400ms	49	50	98.00
V2	stress_all	spi_host_stress_all	3.150m	12.527ms	50	50	100.00
V2	spien	spi_host_spien	9.667m	108.630ms	50	50	100.00
V2	stall	spi_host_status_stall	9.683m	165.086ms	44	50	88.00
V2	Idlecsbactive	spi_host_idlecsbactive	38.000s	5.473ms	50	50	100.00
V2	alert_test	spi_host_alert_test	7.000s	45.417us	50	50	100.00
V2	intr_test	spi_host_intr_test	7.000s	16.464us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	5.000s	467.613us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	5.000s	467.613us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	3.000s	18.385us	5	5	100.00
		spi_host_csr_rw	4.000s	22.617us	20	20	100.00
		spi_host_csr_aliasing	3.000s	80.036us	5	5	100.00
		spi_host_same_csr_outstanding	4.000s	149.217us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	3.000s	18.385us	5	5	100.00
		spi_host_csr_rw	4.000s	22.617us	20	20	100.00
		spi_host_csr_aliasing	3.000s	80.036us	5	5	100.00
		spi_host_same_csr_outstanding	4.000s	149.217us	20	20	100.00
V2		TOTAL			681	690	98.70
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	61.170us	20	20	100.00
		spi_host_sec_cm	3.000s	72.956us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	61.170us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	winbond	winbond			0	0	--
V3	stress_all_with_rand_reset	spi_host_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			820	830	98.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	15	15	12	80.00
V2S	2	2	2	100.00
V3	2	0	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.07	98.13	95.98	99.73	96.61	95.70	100.00	98.60	90.87

Failure Buckets

UVM_FATAL (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 6 failures:
- Test spi_host_overflow_underflow has 2 failures.
  - 5.spi_host_overflow_underflow.1204822178541026707144888835908400773341414966052982657698645191426368442160
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_overflow_underflow/latest/run.log
```
  UVM_FATAL @ 28199893603 ps: (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x5d919c14) == 0x0
  UVM_INFO @ 28199893603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 49.spi_host_overflow_underflow.15273820850395538687437816591881864773098974762466877455212290145830507660104
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/49.spi_host_overflow_underflow/latest/run.log
```
  UVM_FATAL @ 43730867031 ps: (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xc5151e54) == 0x0
  UVM_INFO @ 43730867031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_status_stall has 3 failures.
  - 13.spi_host_status_stall.109349229387412659160433127167552677427886175677688953576580228423138454631141
    Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/13.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 165085765271 ps: (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x92661cd4) == 0x0
  UVM_INFO @ 165085765271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 24.spi_host_status_stall.69004324721196312259854035354538699109621571643558482844195791481730868206499
    Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/24.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 102038329857 ps: (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x348a3f54) == 0x0
  UVM_INFO @ 102038329857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test spi_host_sw_reset has 1 failures.
  - 16.spi_host_sw_reset.111437739031043471790607980645162887428499007972977225159901651581340538282792
    Line 301, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/16.spi_host_sw_reset/latest/run.log
```
  UVM_FATAL @ 26300878886 ps: (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x40d5ce94) == 0x0
  UVM_INFO @ 26300878886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 2 failures:
- Test spi_host_smoke has 1 failures.
  - 10.spi_host_smoke.84822678656599895500235275848561386673591241840184220740826134909090716024855
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 162179164346 ps: (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xfde52914) == 0x0
  UVM_INFO @ 162179164346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_status_stall has 1 failures.
  - 22.spi_host_status_stall.44076206075074812344229845450194335588023066093268583373580890363375347560679
    Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/22.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 143896385551 ps: (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xcba2df94) == 0x0
  UVM_INFO @ 143896385551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 2 failures:
- Test spi_host_status_stall has 2 failures.
  - 20.spi_host_status_stall.84790019155046933543374472136655803557450103986274429868375913221333458788489
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/20.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 36228943768 ps: (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x24f41dd4) == 0x1
  UVM_INFO @ 36228943768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 27.spi_host_status_stall.1182219762464335249187059388183014473401556967213614890949772925566111230817
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/27.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 18812524740 ps: (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xa0a05bd4) == 0x1
  UVM_INFO @ 18812524740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SPI_HOST Simulation Results

Thursday February 29 2024 20:02:24 UTC

GitHub Revision: e0c4026501

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 37435771356197831901593787335841447308974032110687249165442170486932885997295

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `e0c4026501`