SPI_HOST Simulation Results

Sunday March 03 2024 20:02:47 UTC

GitHub Revision: `0cdf265eaa`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 82530437672810453765703374940713112405319051694331588453064008042331386550559

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	10.833m	13.744ms	49	50	98.00
V1	csr_hw_reset	spi_host_csr_hw_reset	3.000s	20.229us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	7.000s	35.303us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	2.193ms	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	3.000s	34.308us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	26.665us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	7.000s	35.303us	20	20	100.00
		spi_host_csr_aliasing	3.000s	34.308us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	3.000s	32.260us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	3.000s	27.969us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	performance	spi_host_performance	6.000s	32.004us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	3.483m	12.877ms	49	50	98.00
		spi_host_error_cmd	5.000s	17.772us	50	50	100.00
		spi_host_event	26.250m	37.982ms	50	50	100.00
V2	clock_rate	spi_host_speed	6.483m	8.111ms	50	50	100.00
V2	speed	spi_host_speed	6.483m	8.111ms	50	50	100.00
V2	chip_select_timing	spi_host_speed	6.483m	8.111ms	50	50	100.00
V2	sw_reset	spi_host_sw_reset	4.917m	10.174ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	7.000s	188.054us	50	50	100.00
V2	cpol_cpha	spi_host_speed	6.483m	8.111ms	50	50	100.00
V2	full_cycle	spi_host_speed	6.483m	8.111ms	50	50	100.00
V2	duplex	spi_host_smoke	10.833m	13.744ms	49	50	98.00
V2	tx_rx_only	spi_host_smoke	10.833m	13.744ms	49	50	98.00
V2	stress_all	spi_host_stress_all	3.617m	11.430ms	49	50	98.00
V2	spien	spi_host_spien	7.600m	39.286ms	47	50	94.00
V2	stall	spi_host_status_stall	11.117m	54.178ms	47	50	94.00
V2	Idlecsbactive	spi_host_idlecsbactive	48.000s	13.780ms	49	50	98.00
V2	alert_test	spi_host_alert_test	6.000s	16.185us	50	50	100.00
V2	intr_test	spi_host_intr_test	3.000s	15.244us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	4.000s	46.746us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	4.000s	46.746us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	3.000s	20.229us	5	5	100.00
		spi_host_csr_rw	7.000s	35.303us	20	20	100.00
		spi_host_csr_aliasing	3.000s	34.308us	5	5	100.00
		spi_host_same_csr_outstanding	3.000s	38.216us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	3.000s	20.229us	5	5	100.00
		spi_host_csr_rw	7.000s	35.303us	20	20	100.00
		spi_host_csr_aliasing	3.000s	34.308us	5	5	100.00
		spi_host_same_csr_outstanding	3.000s	38.216us	20	20	100.00
V2		TOTAL			681	690	98.70
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	147.548us	20	20	100.00
		spi_host_sec_cm	3.000s	40.974us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	147.548us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	winbond	winbond			0	0	--
V3	stress_all_with_rand_reset	spi_host_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			820	830	98.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	15	15	10	66.67
V2S	2	2	2	100.00
V3	2	0	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.05	98.13	95.98	99.73	96.52	95.70	100.00	98.60	90.87

Failure Buckets

UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 5 failures:
- Test spi_host_status_stall has 2 failures.
  - 7.spi_host_status_stall.2666564253623501048274668300681472261180031110297936193804186309513102192682
    Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 38686548256 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xded94cd4) == 0x0
  UVM_INFO @ 38686548256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 34.spi_host_status_stall.82647543457024736105531198347559762481729340487470455791410582532369723100096
    Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/34.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 171476440959 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xbc15fd14) == 0x0
  UVM_INFO @ 171476440959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_overflow_underflow has 1 failures.
  - 10.spi_host_overflow_underflow.80885499015355555358639276699468760508959296747346342076713422177116998385243
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_overflow_underflow/latest/run.log
```
  UVM_FATAL @ 43881244020 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xb0e4f014) == 0x0
  UVM_INFO @ 43881244020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_idlecsbactive has 1 failures.
  - 25.spi_host_idlecsbactive.20684820139104825359062837449896481587577799075834720057280602117783707016251
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/25.spi_host_idlecsbactive/latest/run.log
```
  UVM_FATAL @ 10052605399 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x7d4ee1d4) == 0x0
  UVM_INFO @ 10052605399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_smoke has 1 failures.
  - 35.spi_host_smoke.16981209775799009818519181327478195567031374817768620997300318302544341444044
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/35.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 138160764393 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xc0bc7554) == 0x0
  UVM_INFO @ 138160764393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 2 failures:
- Test spi_host_status_stall has 1 failures.
  - 17.spi_host_status_stall.9627296006745985271046517704284900029024122151866167334401415017242973881563
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/17.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 38771805531 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xa39be914) == 0x1
  UVM_INFO @ 38771805531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_spien has 1 failures.
  - 48.spi_host_spien.34292632374610859319903412092171033128744726932100826465213320619254404711558
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/48.spi_host_spien/latest/run.log
```
  UVM_FATAL @ 56246991979 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x721c1194) == 0x1
  UVM_INFO @ 56246991979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 1 failures:
- Test spi_host_stress_all has 1 failures.
  - 4.spi_host_stress_all.3731109284986430578799696385396657252959815538927146062233834105616591865888
    Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_stress_all/latest/run.log
```
  UVM_FATAL @ 18297429162 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x691114d4) == 0x0
  UVM_INFO @ 18297429162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 1 failures:
- Test spi_host_spien has 1 failures.
  - 8.spi_host_spien.56911477204637979991916907917393242933119325094667834222858260267803275035424
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_spien/latest/run.log
```
  UVM_FATAL @ 10014454902 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xcc03a414) == 0x0
  UVM_INFO @ 10014454902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 1 failures:
- Test spi_host_spien has 1 failures.
  - 42.spi_host_spien.23864665232154758336086265078202065423473423751726749295820629082816321921243
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/42.spi_host_spien/latest/run.log
```
  UVM_FATAL @ 26797235155 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x76c037d4) == 0x1
  UVM_INFO @ 26797235155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SPI_HOST Simulation Results

Sunday March 03 2024 20:02:47 UTC

GitHub Revision: 0cdf265eaa

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 82530437672810453765703374940713112405319051694331588453064008042331386550559

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `0cdf265eaa`