SPI_HOST Simulation Results

Tuesday March 05 2024 20:02:48 UTC

GitHub Revision: `c30684b3ca`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 61875946985821051720030118255902427822651914203242934898647746371735217685454

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	10.017m	48.982ms	48	50	96.00
V1	csr_hw_reset	spi_host_csr_hw_reset	3.000s	40.830us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	4.000s	109.401us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	235.153us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	3.000s	96.250us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	325.797us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	4.000s	109.401us	20	20	100.00
		spi_host_csr_aliasing	3.000s	96.250us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	3.000s	26.580us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	3.000s	23.757us	5	5	100.00
V1		TOTAL			113	115	98.26
V2	performance	spi_host_performance	4.000s	97.491us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	2.817m	3.459ms	50	50	100.00
		spi_host_error_cmd	3.000s	104.418us	50	50	100.00
		spi_host_event	18.367m	41.524ms	50	50	100.00
V2	clock_rate	spi_host_speed	7.750m	9.627ms	50	50	100.00
V2	speed	spi_host_speed	7.750m	9.627ms	50	50	100.00
V2	chip_select_timing	spi_host_speed	7.750m	9.627ms	50	50	100.00
V2	sw_reset	spi_host_sw_reset	5.900m	12.284ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	3.000s	535.899us	50	50	100.00
V2	cpol_cpha	spi_host_speed	7.750m	9.627ms	50	50	100.00
V2	full_cycle	spi_host_speed	7.750m	9.627ms	50	50	100.00
V2	duplex	spi_host_smoke	10.017m	48.982ms	48	50	96.00
V2	tx_rx_only	spi_host_smoke	10.017m	48.982ms	48	50	96.00
V2	stress_all	spi_host_stress_all	5.483m	45.067ms	48	50	96.00
V2	spien	spi_host_spien	5.617m	7.486ms	48	50	96.00
V2	stall	spi_host_status_stall	10.000m	26.878ms	48	50	96.00
V2	Idlecsbactive	spi_host_idlecsbactive	43.000s	16.441ms	50	50	100.00
V2	alert_test	spi_host_alert_test	3.000s	49.388us	50	50	100.00
V2	intr_test	spi_host_intr_test	7.000s	29.417us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	5.000s	32.410us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	5.000s	32.410us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	3.000s	40.830us	5	5	100.00
		spi_host_csr_rw	4.000s	109.401us	20	20	100.00
		spi_host_csr_aliasing	3.000s	96.250us	5	5	100.00
		spi_host_same_csr_outstanding	8.000s	54.015us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	3.000s	40.830us	5	5	100.00
		spi_host_csr_rw	4.000s	109.401us	20	20	100.00
		spi_host_csr_aliasing	3.000s	96.250us	5	5	100.00
		spi_host_same_csr_outstanding	8.000s	54.015us	20	20	100.00
V2		TOTAL			684	690	99.13
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	93.494us	20	20	100.00
		spi_host_sec_cm	3.000s	65.477us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	93.494us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	winbond	winbond			0	0	--
V3	stress_all_with_rand_reset	spi_host_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			822	830	99.04

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	15	15	12	80.00
V2S	2	2	2	100.00
V3	2	0	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.07	98.13	95.98	99.73	96.61	95.70	100.00	98.60	90.87

Failure Buckets

UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 4 failures:
- Test spi_host_status_stall has 2 failures.
  - 15.spi_host_status_stall.49309190389842646816613532625036686519187503671611689453598845096080221795123
    Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/15.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 156404772227 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x6e3ff894) == 0x0
  UVM_INFO @ 156404772227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 49.spi_host_status_stall.25617001627628178163097517428829943357205933057507187838790748519610624015792
    Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/49.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 86761329102 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xd4617ad4) == 0x0
  UVM_INFO @ 86761329102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_stress_all has 2 failures.
  - 25.spi_host_stress_all.101873198456340590277075057788022724134690153907738775780050888875644697215057
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/25.spi_host_stress_all/latest/run.log
```
  UVM_FATAL @ 22631808810 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xf22da54) == 0x0
  UVM_INFO @ 22631808810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 31.spi_host_stress_all.91917377961157390856450131013597152985046102813780872782032739743263771776578
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/31.spi_host_stress_all/latest/run.log
```
  UVM_FATAL @ 18127856751 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x894adf14) == 0x0
  UVM_INFO @ 18127856751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 2 failures:
- Test spi_host_smoke has 2 failures.
  - 7.spi_host_smoke.22608718646534961337500923324466369940422443760073210590877270757592723564166
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 101927834651 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x298dae54) == 0x0
  UVM_INFO @ 101927834651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 21.spi_host_smoke.39728891011195350845905590258855708007729504630200748176136148307198033776215
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/21.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 156189844796 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x5dc92954) == 0x0
  UVM_INFO @ 156189844796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 1 failures:
- Test spi_host_spien has 1 failures.
  - 17.spi_host_spien.32358505375498430651003064913427263534944575426332821881873605641437368881402
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/17.spi_host_spien/latest/run.log
```
  UVM_FATAL @ 10005955509 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x18860dd4) == 0x0
  UVM_INFO @ 10005955509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 1 failures:
- Test spi_host_spien has 1 failures.
  - 20.spi_host_spien.51159524369982878402449243474510399190767591479929987952660006114317304130456
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/20.spi_host_spien/latest/run.log
```
  UVM_FATAL @ 34172568131 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x96d24cd4) == 0x1
  UVM_INFO @ 34172568131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SPI_HOST Simulation Results

Tuesday March 05 2024 20:02:48 UTC

GitHub Revision: c30684b3ca

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 61875946985821051720030118255902427822651914203242934898647746371735217685454

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `c30684b3ca`