SPI_HOST Simulation Results

Thursday March 07 2024 20:02:34 UTC

GitHub Revision: `36c168c253`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 132539995404104259171688804297348475616986265371189902218943342622053800053

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	9.667m	49.821ms	46	50	92.00
V1	csr_hw_reset	spi_host_csr_hw_reset	3.000s	18.632us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	3.000s	16.624us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	4.000s	58.997us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	3.000s	72.070us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	36.781us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	3.000s	16.624us	20	20	100.00
		spi_host_csr_aliasing	3.000s	72.070us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	3.000s	36.870us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	5.000s	41.742us	5	5	100.00
V1		TOTAL			111	115	96.52
V2	performance	spi_host_performance	6.000s	88.056us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	3.483m	17.579ms	50	50	100.00
		spi_host_error_cmd	5.000s	32.090us	50	50	100.00
		spi_host_event	15.933m	68.973ms	50	50	100.00
V2	clock_rate	spi_host_speed	4.050m	10.244ms	24	50	48.00
V2	speed	spi_host_speed	4.050m	10.244ms	24	50	48.00
V2	chip_select_timing	spi_host_speed	4.050m	10.244ms	24	50	48.00
V2	sw_reset	spi_host_sw_reset	8.200m	16.921ms	42	50	84.00
V2	passthrough_mode	spi_host_passthrough_mode	6.000s	872.154us	50	50	100.00
V2	cpol_cpha	spi_host_speed	4.050m	10.244ms	24	50	48.00
V2	full_cycle	spi_host_speed	4.050m	10.244ms	24	50	48.00
V2	duplex	spi_host_smoke	9.667m	49.821ms	46	50	92.00
V2	tx_rx_only	spi_host_smoke	9.667m	49.821ms	46	50	92.00
V2	stress_all	spi_host_stress_all	4.233m	10.002ms	45	50	90.00
V2	spien	spi_host_spien	6.083m	7.673ms	38	50	76.00
V2	stall	spi_host_status_stall	9.567m	47.537ms	26	50	52.00
V2	Idlecsbactive	spi_host_idlecsbactive	38.000s	10.027ms	37	50	74.00
V2	alert_test	spi_host_alert_test	6.000s	31.496us	50	50	100.00
V2	intr_test	spi_host_intr_test	3.000s	54.077us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	5.000s	153.898us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	5.000s	153.898us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	3.000s	18.632us	5	5	100.00
		spi_host_csr_rw	3.000s	16.624us	20	20	100.00
		spi_host_csr_aliasing	3.000s	72.070us	5	5	100.00
		spi_host_same_csr_outstanding	4.000s	19.311us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	3.000s	18.632us	5	5	100.00
		spi_host_csr_rw	3.000s	16.624us	20	20	100.00
		spi_host_csr_aliasing	3.000s	72.070us	5	5	100.00
		spi_host_same_csr_outstanding	4.000s	19.311us	20	20	100.00
V2		TOTAL			602	690	87.25
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	148.252us	20	20	100.00
		spi_host_sec_cm	3.000s	238.507us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	148.252us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	winbond	winbond			0	0	--
V3	stress_all_with_rand_reset	spi_host_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			738	830	88.92

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	15	15	9	60.00
V2S	2	2	2	100.00
V3	2	0	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.09	98.13	95.98	99.73	96.79	95.70	100.00	98.60	90.87

Failure Buckets

UVM_FATAL (spi_host_scoreboard.sv:147) scoreboard [scoreboard] has 63 failures:

Test spi_host_sw_reset has 7 failures.

1.spi_host_sw_reset.109472442468177980324546067871032279147733138207545771989184653413613303629637
Line 343, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_sw_reset/latest/run.log

  UVM_FATAL @ 3759790954 ps: (spi_host_scoreboard.sv:147) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
       WRITE: actual data did not match exp data
   len          4
       byte      actual     expected
        [          0]              60              60

8.spi_host_sw_reset.30053237560410942263560519646458463118336360984729687823738724220822059717447
Line 280, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_sw_reset/latest/run.log

  UVM_FATAL @ 2132096894 ps: (spi_host_scoreboard.sv:147) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
       WRITE: actual data did not match exp data
   len          4
       byte      actual     expected
        [          0]              dc              dc

... and 5 more failures.

Test spi_host_status_stall has 16 failures.

1.spi_host_status_stall.109352930293726444074924782085281869428348538067382023880701309717563937097927
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_status_stall/latest/run.log

  UVM_FATAL @ 228366844 ps: (spi_host_scoreboard.sv:147) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
       WRITE: actual data did not match exp data
   len          4
       byte      actual     expected
        [          0]              cc              cc

5.spi_host_status_stall.103345197487569320662382426886003305827542104116067238033468604261739256475323
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_status_stall/latest/run.log

  UVM_FATAL @ 2090724005 ps: (spi_host_scoreboard.sv:147) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
       WRITE: actual data did not match exp data
   len          4
       byte      actual     expected
        [          0]              52              52

... and 14 more failures.

Test spi_host_idlecsbactive has 12 failures.

1.spi_host_idlecsbactive.95751326562678103896194470491063990604347863590925981890412723038170944660372
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_idlecsbactive/latest/run.log

  UVM_FATAL @ 2395180631 ps: (spi_host_scoreboard.sv:147) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
       WRITE: actual data did not match exp data
   len          4
       byte      actual     expected
        [          0]              cc              cc

2.spi_host_idlecsbactive.41625255087265217106811566421520654039331303927106197141988892844065419558922
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_idlecsbactive/latest/run.log

  UVM_FATAL @  68085151 ps: (spi_host_scoreboard.sv:147) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
       WRITE: actual data did not match exp data
   len          4
       byte      actual     expected
        [          0]              cc              cc

... and 10 more failures.

Test spi_host_speed has 17 failures.

4.spi_host_speed.52426386437681644733933294794482263596576813876372403929978620272581416581147
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_speed/latest/run.log

  UVM_FATAL @ 7623107455 ps: (spi_host_scoreboard.sv:147) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
       WRITE: actual data did not match exp data
   len          4
       byte      actual     expected
        [          0]              3              3

5.spi_host_speed.13883075206009026929559925983505408731922237431952779495563690579559405690761
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_speed/latest/run.log

  UVM_FATAL @ 106375553 ps: (spi_host_scoreboard.sv:147) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
       WRITE: actual data did not match exp data
   len          4
       byte      actual     expected
        [          0]              f              f

... and 15 more failures.

Test spi_host_spien has 9 failures.

6.spi_host_spien.94801772955233117781515820153514706304333735071622546083375858529276311674212
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_spien/latest/run.log

  UVM_FATAL @ 10198997210 ps: (spi_host_scoreboard.sv:147) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
       WRITE: actual data did not match exp data
   len          4
       byte      actual     expected
        [          0]              15              15

11.spi_host_spien.61271561032985268866849411133290693487719777018625839754170946841852929208826
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/11.spi_host_spien/latest/run.log

  UVM_FATAL @ 421517292 ps: (spi_host_scoreboard.sv:147) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
       WRITE: actual data did not match exp data
   len          4
       byte      actual     expected
        [          0]              78              78

... and 7 more failures.

... and 1 more tests.

Exit reason: Error: User command failed UVM_FATAL (spi_host_scoreboard.sv:147) scoreboard [scoreboard] has 21 failures:

Test spi_host_status_stall has 8 failures.

2.spi_host_status_stall.39224058872417008093735898214535946847634244326857983191698385557131301311793
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_status_stall/latest/run.log

  UVM_FATAL @ 17814966665 ps: (spi_host_scoreboard.sv:147) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
       WRITE: actual data did not match exp data
   len          6
       byte      actual     expected
        [          0]              89              89

8.spi_host_status_stall.80551702836526832306885032394097191345372217894746734701780562977164751064453
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_status_stall/latest/run.log

  UVM_FATAL @ 2582290812 ps: (spi_host_scoreboard.sv:147) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
       WRITE: actual data did not match exp data
   len          4
       byte      actual     expected
        [          0]              bd              bd

... and 6 more failures.

Test spi_host_spien has 2 failures.

3.spi_host_spien.50045296839030263078935534133542677053253964148327502353226581289652117037298
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_spien/latest/run.log

  UVM_FATAL @ 190872791 ps: (spi_host_scoreboard.sv:147) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
       WRITE: actual data did not match exp data
   len          4
       byte      actual     expected
        [          0]              cc              cc

26.spi_host_spien.100139156948188251008735758768371860610534618053509547970579381757964028708161
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/26.spi_host_spien/latest/run.log

  UVM_FATAL @ 326324042 ps: (spi_host_scoreboard.sv:147) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
       WRITE: actual data did not match exp data
   len          4
       byte      actual     expected
        [          0]              cc              cc

Test spi_host_speed has 9 failures.

6.spi_host_speed.95662913892467766858473784374679111689677569476665616836533271564385339012348
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_speed/latest/run.log

  UVM_FATAL @ 467986680 ps: (spi_host_scoreboard.sv:147) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
       WRITE: actual data did not match exp data
   len          4
       byte      actual     expected
        [          0]              3              3

11.spi_host_speed.27668753018853314432966075722410996689410454981672919787769697599498490080680
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/11.spi_host_speed/latest/run.log

  UVM_FATAL @ 957373581 ps: (spi_host_scoreboard.sv:147) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
       WRITE: actual data did not match exp data
   len          6
       byte      actual     expected
        [          0]              d3              d3

... and 7 more failures.

Test spi_host_stress_all has 1 failures.

15.spi_host_stress_all.63998668380821018334647971252016863098585846348419224776359082347286895495999
Line 280, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/15.spi_host_stress_all/latest/run.log

  UVM_FATAL @ 348890750 ps: (spi_host_scoreboard.sv:147) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
       WRITE: actual data did not match exp data
   len          4
       byte      actual     expected
        [          0]              3              3

Test spi_host_sw_reset has 1 failures.

29.spi_host_sw_reset.101279000707880409609204018889397432227427389765335031719134733479800651443218
Line 280, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/29.spi_host_sw_reset/latest/run.log

  UVM_FATAL @ 2127749848 ps: (spi_host_scoreboard.sv:147) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
       WRITE: actual data did not match exp data
   len          4
       byte      actual     expected
        [          0]              63              63

UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 4 failures:
- Test spi_host_idlecsbactive has 1 failures.
  - 0.spi_host_idlecsbactive.39121105610681942521008601748387788344431032100775841067689166587373419113707
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_idlecsbactive/latest/run.log
```
  UVM_FATAL @ 10026524863 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x10f0e114) == 0x0
  UVM_INFO @ 10026524863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_smoke has 3 failures.
  - 5.spi_host_smoke.50833658299530542270562743396544294006306087856846974223091116376494240473800
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 75283544082 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xdae6dc94) == 0x0
  UVM_INFO @ 75283544082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 39.spi_host_smoke.55346134093246326357467226161398294798847398923657737348102103752640213486366
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/39.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 125841525716 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x139381d4) == 0x0
  UVM_INFO @ 125841525716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 3 failures:
- Test spi_host_stress_all has 2 failures.
  - 32.spi_host_stress_all.4953982629745298595085471575247408828856027627421256724652310576438370024638
    Line 280, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/32.spi_host_stress_all/latest/run.log
```
  UVM_FATAL @ 10001617643 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x26cd5554) == 0x0
  UVM_INFO @ 10001617643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 43.spi_host_stress_all.90540185437874082169091844983925017023095940477546718800784811343773222723463
    Line 315, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/43.spi_host_stress_all/latest/run.log
```
  UVM_FATAL @ 11791291477 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x68207fd4) == 0x0
  UVM_INFO @ 11791291477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_spien has 1 failures.
  - 33.spi_host_spien.92297009994653226303429935472089380596687529318876219246594754308637793198341
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/33.spi_host_spien/latest/run.log
```
  UVM_FATAL @ 10015728695 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xa16f4314) == 0x0
  UVM_INFO @ 10015728695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 1 failures:
- Test spi_host_smoke has 1 failures.
  - 6.spi_host_smoke.81686068189483570726177466531285718198226066268834207381158527180494937392209
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 60282362534 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xe329e754) == 0x0
  UVM_INFO @ 60282362534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```