SPI_HOST Simulation Results

Sunday March 10 2024 19:02:34 UTC

GitHub Revision: `8d1fda3660`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 55344925760588090643748974780216117977546302496149780891974223483299136808506

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	10.183m	52.141ms	49	50	98.00
V1	csr_hw_reset	spi_host_csr_hw_reset	4.000s	18.623us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	3.000s	25.473us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	731.453us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	3.000s	43.489us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	6.000s	20.398us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	3.000s	25.473us	20	20	100.00
		spi_host_csr_aliasing	3.000s	43.489us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	6.000s	92.400us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	4.000s	88.139us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	performance	spi_host_performance	7.000s	35.740us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	3.400m	8.198ms	50	50	100.00
		spi_host_error_cmd	6.000s	38.441us	50	50	100.00
		spi_host_event	23.850m	124.565ms	50	50	100.00
V2	clock_rate	spi_host_speed	4.400m	31.648ms	50	50	100.00
V2	speed	spi_host_speed	4.400m	31.648ms	50	50	100.00
V2	chip_select_timing	spi_host_speed	4.400m	31.648ms	50	50	100.00
V2	sw_reset	spi_host_sw_reset	8.767m	40.246ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	7.000s	541.501us	50	50	100.00
V2	cpol_cpha	spi_host_speed	4.400m	31.648ms	50	50	100.00
V2	full_cycle	spi_host_speed	4.400m	31.648ms	50	50	100.00
V2	duplex	spi_host_smoke	10.183m	52.141ms	49	50	98.00
V2	tx_rx_only	spi_host_smoke	10.183m	52.141ms	49	50	98.00
V2	stress_all	spi_host_stress_all	5.083m	30.639ms	48	50	96.00
V2	spien	spi_host_spien	6.283m	14.443ms	49	50	98.00
V2	stall	spi_host_status_stall	11.750m	15.435ms	45	50	90.00
V2	Idlecsbactive	spi_host_idlecsbactive	44.000s	2.600ms	49	50	98.00
V2	alert_test	spi_host_alert_test	7.000s	18.949us	50	50	100.00
V2	intr_test	spi_host_intr_test	5.000s	28.436us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	8.000s	93.285us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	8.000s	93.285us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	4.000s	18.623us	5	5	100.00
		spi_host_csr_rw	3.000s	25.473us	20	20	100.00
		spi_host_csr_aliasing	3.000s	43.489us	5	5	100.00
		spi_host_same_csr_outstanding	5.000s	104.095us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	4.000s	18.623us	5	5	100.00
		spi_host_csr_rw	3.000s	25.473us	20	20	100.00
		spi_host_csr_aliasing	3.000s	43.489us	5	5	100.00
		spi_host_same_csr_outstanding	5.000s	104.095us	20	20	100.00
V2		TOTAL			681	690	98.70
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	83.833us	20	20	100.00
		spi_host_sec_cm	3.000s	99.340us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	83.833us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	winbond	winbond			0	0	--
V3	stress_all_with_rand_reset	spi_host_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			820	830	98.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	15	15	11	73.33
V2S	2	2	2	100.00
V3	2	0	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.08	98.13	95.98	99.73	96.70	95.70	100.00	98.60	90.87

Failure Buckets

UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 5 failures:
- Test spi_host_status_stall has 3 failures.
  - 7.spi_host_status_stall.115138937535158517526083334750214700138318921722585435427448893811365572678
    Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 69523696767 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x7214a54) == 0x0
  UVM_INFO @ 69523696767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 18.spi_host_status_stall.107120656798122394405589176140283600428425097651398097164946752610594484410439
    Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/18.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 55902028722 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x51a12894) == 0x0
  UVM_INFO @ 55902028722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test spi_host_idlecsbactive has 1 failures.
  - 26.spi_host_idlecsbactive.1566963659277880334832440642496173657570075308097893300669095864776565175745
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/26.spi_host_idlecsbactive/latest/run.log
```
  UVM_FATAL @ 10067819311 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x3396e854) == 0x0
  UVM_INFO @ 10067819311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_stress_all has 1 failures.
  - 41.spi_host_stress_all.25858932795494732335334936572196800593282377852270768596940583750142113322323
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/41.spi_host_stress_all/latest/run.log
```
  UVM_FATAL @ 14028425733 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x7f0a4ed4) == 0x0
  UVM_INFO @ 14028425733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 3 failures:
- Test spi_host_spien has 1 failures.
  - 13.spi_host_spien.83570466817672624413809258020030339691794058842694432602637677307369719423229
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/13.spi_host_spien/latest/run.log
```
  UVM_FATAL @ 32899027342 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x34010994) == 0x1
  UVM_INFO @ 32899027342 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_status_stall has 2 failures.
  - 38.spi_host_status_stall.65746815581697581224250907466664756775069309852227071668619772232864762159784
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/38.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 15434957063 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x1b250ad4) == 0x1
  UVM_INFO @ 15434957063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 42.spi_host_status_stall.92498545649598018438250620346054199925259400136776179602640217640180908144753
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/42.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 64239927491 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x6b9c5414) == 0x1
  UVM_INFO @ 64239927491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 1 failures:
- Test spi_host_smoke has 1 failures.
  - 1.spi_host_smoke.31370822322859918272404758803019232161421226070255079167209709291632204298133
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 10016330437 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xfcbcbbd4) == 0x0
  UVM_INFO @ 10016330437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 1 failures:
- Test spi_host_stress_all has 1 failures.
  - 9.spi_host_stress_all.88366314613048669098850655450497505135585283391106936813784244795543089647651
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_stress_all/latest/run.log
```
  UVM_FATAL @ 10004828428 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xecd3ab14) == 0x0
  UVM_INFO @ 10004828428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SPI_HOST Simulation Results

Sunday March 10 2024 19:02:34 UTC

GitHub Revision: 8d1fda3660

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 55344925760588090643748974780216117977546302496149780891974223483299136808506

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `8d1fda3660`