SPI_HOST Simulation Results

Tuesday March 12 2024 19:02:37 UTC

GitHub Revision: bc285b7382

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 8078106501385188224785993882809517173695187907049792415947230968390919037084

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	9.317m	22.684ms	48	50	96.00
V1	csr_hw_reset	spi_host_csr_hw_reset	5.000s	19.355us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	6.000s	29.387us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	8.000s	235.604us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	10.000s	62.082us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	11.000s	93.645us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	6.000s	29.387us	20	20	100.00
		spi_host_csr_aliasing	10.000s	62.082us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	5.000s	41.428us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	4.000s	40.062us	5	5	100.00
V1		TOTAL			113	115	98.26
V2	performance	spi_host_performance	4.000s	174.316us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	2.800m	13.047ms	50	50	100.00
		spi_host_error_cmd	7.000s	18.164us	50	50	100.00
		spi_host_event	18.417m	49.550ms	50	50	100.00
V2	clock_rate	spi_host_speed	6.517m	73.661ms	50	50	100.00
V2	speed	spi_host_speed	6.517m	73.661ms	50	50	100.00
V2	chip_select_timing	spi_host_speed	6.517m	73.661ms	50	50	100.00
V2	sw_reset	spi_host_sw_reset	15.183m	45.742ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	3.000s	238.396us	50	50	100.00
V2	cpol_cpha	spi_host_speed	6.517m	73.661ms	50	50	100.00
V2	full_cycle	spi_host_speed	6.517m	73.661ms	50	50	100.00
V2	duplex	spi_host_smoke	9.317m	22.684ms	48	50	96.00
V2	tx_rx_only	spi_host_smoke	9.317m	22.684ms	48	50	96.00
V2	stress_all	spi_host_stress_all	5.433m	22.387ms	48	50	96.00
V2	spien	spi_host_spien	7.067m	69.241ms	49	50	98.00
V2	stall	spi_host_status_stall	8.700m	49.369ms	49	50	98.00
V2	Idlecsbactive	spi_host_idlecsbactive	45.000s	9.718ms	50	50	100.00
V2	alert_test	spi_host_alert_test	7.000s	18.595us	50	50	100.00
V2	intr_test	spi_host_intr_test	14.000s	17.964us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	9.000s	107.851us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	9.000s	107.851us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	5.000s	19.355us	5	5	100.00
		spi_host_csr_rw	6.000s	29.387us	20	20	100.00
		spi_host_csr_aliasing	10.000s	62.082us	5	5	100.00
		spi_host_same_csr_outstanding	6.000s	23.549us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	5.000s	19.355us	5	5	100.00
		spi_host_csr_rw	6.000s	29.387us	20	20	100.00
		spi_host_csr_aliasing	10.000s	62.082us	5	5	100.00
		spi_host_same_csr_outstanding	6.000s	23.549us	20	20	100.00
V2		TOTAL			686	690	99.42
V2S	tl_intg_err	spi_host_tl_intg_err	7.000s	468.622us	20	20	100.00
		spi_host_sec_cm	3.000s	44.410us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	7.000s	468.622us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	winbond	winbond			0	0	--
V3	stress_all_with_rand_reset	spi_host_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			824	830	99.28

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	15	15	12	80.00
V2S	2	2	2	100.00
V3	2	0	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.08	98.13	95.98	99.73	96.70	95.70	100.00	98.60	90.87

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 4 failures:

  • Test spi_host_status_stall has 1 failures.

    • 5.spi_host_status_stall.75392996700274476479387848591217493007274982639173566314412941710592154407788
      Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_status_stall/latest/run.log

        UVM_FATAL @ 117210116278 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xee5562d4) == 0x0
        UVM_INFO @ 117210116278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test spi_host_smoke has 2 failures.

    • 8.spi_host_smoke.14549891994954478436823497308900732768507790790317155528628890107693543945763
      Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_smoke/latest/run.log

        UVM_FATAL @ 117585923138 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x3cd52b14) == 0x0
        UVM_INFO @ 117585923138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 11.spi_host_smoke.92053775847399857770000069407044590438922231017160010927320156987375527772566
      Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/11.spi_host_smoke/latest/run.log

        UVM_FATAL @ 65638605610 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x909b9f54) == 0x0
        UVM_INFO @ 65638605610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test spi_host_stress_all has 1 failures.

    • 22.spi_host_stress_all.70328390637692042002689824193930721655477042160579207900891938281205896588641
      Line 280, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/22.spi_host_stress_all/latest/run.log

        UVM_FATAL @ 23831985603 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x9cdf6b54) == 0x0
        UVM_INFO @ 23831985603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 1 failures:

  • Test spi_host_stress_all has 1 failures.

    • 2.spi_host_stress_all.58334403523319398328495908850853993901475544483926901907657015883995610769175
      Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_stress_all/latest/run.log

        UVM_FATAL @ 10001003798 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x8ca86694) == 0x0
        UVM_INFO @ 10001003798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 1 failures:

  • Test spi_host_spien has 1 failures.

    • 11.spi_host_spien.112629782771943291528103211169976081578413709448702708602259941956937934928396
      Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/11.spi_host_spien/latest/run.log

        UVM_FATAL @ 27971385279 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xe3311d94) == 0x1
        UVM_INFO @ 27971385279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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