SPI_HOST Simulation Results

Thursday March 14 2024 19:02:18 UTC

GitHub Revision: e844018f2c

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 83239673812975098462159483702727474484560953854893181354811398969250076096082

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 0 50 0.00
V1 csr_hw_reset spi_host_csr_hw_reset 4.000s 17.800us 5 5 100.00
V1 csr_rw spi_host_csr_rw 4.000s 51.513us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 5.000s 559.066us 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 4.000s 23.563us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 4.000s 36.116us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 4.000s 51.513us 20 20 100.00
spi_host_csr_aliasing 4.000s 23.563us 5 5 100.00
V1 mem_walk spi_host_mem_walk 13.000s 37.540us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 3.000s 47.292us 5 5 100.00
V1 TOTAL 65 115 56.52
V2 performance spi_host_performance 0 50 0.00
V2 error_event_intr spi_host_overflow_underflow 0 50 0.00
spi_host_error_cmd 0 50 0.00
spi_host_event 0 50 0.00
V2 clock_rate spi_host_speed 0 50 0.00
V2 speed spi_host_speed 0 50 0.00
V2 chip_select_timing spi_host_speed 0 50 0.00
V2 sw_reset spi_host_sw_reset 0 50 0.00
V2 passthrough_mode spi_host_passthrough_mode 0 50 0.00
V2 cpol_cpha spi_host_speed 0 50 0.00
V2 full_cycle spi_host_speed 0 50 0.00
V2 duplex spi_host_smoke 0 50 0.00
V2 tx_rx_only spi_host_smoke 0 50 0.00
V2 stress_all spi_host_stress_all 0 50 0.00
V2 spien spi_host_spien 0 50 0.00
V2 stall spi_host_status_stall 0 50 0.00
V2 Idlecsbactive spi_host_idlecsbactive 0 50 0.00
V2 alert_test spi_host_alert_test 0 50 0.00
V2 intr_test spi_host_intr_test 5.000s 80.493us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 5.000s 110.201us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 5.000s 110.201us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 4.000s 17.800us 5 5 100.00
spi_host_csr_rw 4.000s 51.513us 20 20 100.00
spi_host_csr_aliasing 4.000s 23.563us 5 5 100.00
spi_host_same_csr_outstanding 4.000s 26.614us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 4.000s 17.800us 5 5 100.00
spi_host_csr_rw 4.000s 51.513us 20 20 100.00
spi_host_csr_aliasing 4.000s 23.563us 5 5 100.00
spi_host_same_csr_outstanding 4.000s 26.614us 20 20 100.00
V2 TOTAL 90 690 13.04
V2S tl_intg_err spi_host_tl_intg_err 4.000s 78.324us 20 20 100.00
spi_host_sec_cm 0 5 0.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 4.000s 78.324us 20 20 100.00
V2S TOTAL 20 25 80.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 175 830 21.08

Testplan Progress

Items Total Written Passing Progress
V1 8 8 7 87.50
V2 15 15 3 20.00
V2S 2 2 1 50.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
97.22 97.01 93.06 100.00 99.36 88.86 -- 100.00 90.04

Failure Buckets

Past Results