SPI_HOST Simulation Results

Sunday March 17 2024 19:02:52 UTC

GitHub Revision: `c187a82ee8`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 28440605375541353837496064678278045899395893237469128852560697715229879921060

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	9.517m	11.637ms	47	50	94.00
V1	csr_hw_reset	spi_host_csr_hw_reset	2.000s	41.867us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	3.000s	24.391us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	108.683us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	3.000s	20.832us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	34.043us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	3.000s	24.391us	20	20	100.00
		spi_host_csr_aliasing	3.000s	20.832us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	3.000s	16.809us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	3.000s	23.302us	5	5	100.00
V1		TOTAL			112	115	97.39
V2	performance	spi_host_performance	7.000s	29.654us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	3.433m	53.980ms	48	50	96.00
		spi_host_error_cmd	12.000s	236.251us	50	50	100.00
		spi_host_event	16.200m	25.042ms	50	50	100.00
V2	clock_rate	spi_host_speed	6.250m	16.220ms	50	50	100.00
V2	speed	spi_host_speed	6.250m	16.220ms	50	50	100.00
V2	chip_select_timing	spi_host_speed	6.250m	16.220ms	50	50	100.00
V2	sw_reset	spi_host_sw_reset	6.317m	13.377ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	13.000s	862.758us	50	50	100.00
V2	cpol_cpha	spi_host_speed	6.250m	16.220ms	50	50	100.00
V2	full_cycle	spi_host_speed	6.250m	16.220ms	50	50	100.00
V2	duplex	spi_host_smoke	9.517m	11.637ms	47	50	94.00
V2	tx_rx_only	spi_host_smoke	9.517m	11.637ms	47	50	94.00
V2	stress_all	spi_host_stress_all	4.800m	6.070ms	48	50	96.00
V2	spien	spi_host_spien	6.550m	46.545ms	50	50	100.00
V2	stall	spi_host_status_stall	10.517m	14.862ms	47	50	94.00
V2	Idlecsbactive	spi_host_idlecsbactive	49.000s	10.698ms	50	50	100.00
V2	alert_test	spi_host_alert_test	12.000s	19.357us	50	50	100.00
V2	intr_test	spi_host_intr_test	12.000s	16.526us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	4.000s	101.751us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	4.000s	101.751us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	2.000s	41.867us	5	5	100.00
		spi_host_csr_rw	3.000s	24.391us	20	20	100.00
		spi_host_csr_aliasing	3.000s	20.832us	5	5	100.00
		spi_host_same_csr_outstanding	3.000s	24.141us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	2.000s	41.867us	5	5	100.00
		spi_host_csr_rw	3.000s	24.391us	20	20	100.00
		spi_host_csr_aliasing	3.000s	20.832us	5	5	100.00
		spi_host_same_csr_outstanding	3.000s	24.141us	20	20	100.00
V2		TOTAL			683	690	98.99
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	105.916us	20	20	100.00
		spi_host_sec_cm	3.000s	141.992us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	105.916us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	winbond	winbond			0	0	--
V3	stress_all_with_rand_reset	spi_host_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			820	830	98.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	15	15	12	80.00
V2S	2	2	2	100.00
V3	2	0	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.08	98.13	95.98	99.73	96.70	95.70	100.00	98.60	90.87

Failure Buckets

UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 8 failures:
- Test spi_host_smoke has 3 failures.
  - 1.spi_host_smoke.73998071444063581298385222767932909980723314326338824117602811994232902568301
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 106313907501 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xabaf5d54) == 0x0
  UVM_INFO @ 106313907501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 47.spi_host_smoke.95074489123267432792865368138921005136226456806901484384807339794167617692929
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/47.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 93054587458 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xa6450214) == 0x0
  UVM_INFO @ 93054587458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test spi_host_overflow_underflow has 2 failures.
  - 10.spi_host_overflow_underflow.22159806703405010087999845643092162733046961677344475595597912509224423232863
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_overflow_underflow/latest/run.log
```
  UVM_FATAL @ 51674822626 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x4c69a054) == 0x0
  UVM_INFO @ 51674822626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 33.spi_host_overflow_underflow.108260125926751625458623942802843790558370956468340044200024246402181097092425
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/33.spi_host_overflow_underflow/latest/run.log
```
  UVM_FATAL @ 53979815611 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x4e692954) == 0x0
  UVM_INFO @ 53979815611 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_status_stall has 2 failures.
  - 13.spi_host_status_stall.37723585962175689246902220932955068274877856641010702567866426885103484501773
    Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/13.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 39410908403 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xabf8d394) == 0x0
  UVM_INFO @ 39410908403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 23.spi_host_status_stall.21584982323717033447404590955133058045372782755251067075244600103985913482241
    Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/23.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 77230652646 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xf48dfe54) == 0x0
  UVM_INFO @ 77230652646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_stress_all has 1 failures.
  - 43.spi_host_stress_all.4954426979709197751259871182706602660671002510201189475316404433965551817749
    Line 280, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/43.spi_host_stress_all/latest/run.log
```
  UVM_FATAL @ 20506512188 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x3995e814) == 0x0
  UVM_INFO @ 20506512188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 1 failures:
- Test spi_host_status_stall has 1 failures.
  - 43.spi_host_status_stall.5468650597145433084745065988238903302993379660706526756709558590940130174171
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/43.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 40330036555 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x8c1c86d4) == 0x1
  UVM_INFO @ 40330036555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 1 failures:
- Test spi_host_stress_all has 1 failures.
  - 48.spi_host_stress_all.68764333032405340090905078540410247472967426072157387420192363107582707024986
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/48.spi_host_stress_all/latest/run.log
```
  UVM_FATAL @ 28713847888 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x1c3485d4) == 0x0
  UVM_INFO @ 28713847888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SPI_HOST Simulation Results

Sunday March 17 2024 19:02:52 UTC

GitHub Revision: c187a82ee8

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 28440605375541353837496064678278045899395893237469128852560697715229879921060

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `c187a82ee8`