SPI_HOST Simulation Results

Tuesday March 19 2024 19:02:40 UTC

GitHub Revision: `f7fc348358`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 93166527750821992054916907919379261408154533955814283538537589225972237641118

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	10.417m	50.459ms	47	50	94.00
V1	csr_hw_reset	spi_host_csr_hw_reset	3.000s	18.465us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	3.000s	27.964us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	437.091us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	4.000s	35.634us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	306.463us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	3.000s	27.964us	20	20	100.00
		spi_host_csr_aliasing	4.000s	35.634us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	5.000s	20.628us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	3.000s	39.351us	5	5	100.00
V1		TOTAL			112	115	97.39
V2	performance	spi_host_performance	3.000s	31.995us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	3.617m	4.592ms	50	50	100.00
		spi_host_error_cmd	3.000s	43.175us	50	50	100.00
		spi_host_event	14.467m	159.744ms	50	50	100.00
V2	clock_rate	spi_host_speed	5.733m	7.484ms	49	50	98.00
V2	speed	spi_host_speed	5.733m	7.484ms	49	50	98.00
V2	chip_select_timing	spi_host_speed	5.733m	7.484ms	49	50	98.00
V2	sw_reset	spi_host_sw_reset	6.550m	21.740ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	4.000s	167.063us	50	50	100.00
V2	cpol_cpha	spi_host_speed	5.733m	7.484ms	49	50	98.00
V2	full_cycle	spi_host_speed	5.733m	7.484ms	49	50	98.00
V2	duplex	spi_host_smoke	10.417m	50.459ms	47	50	94.00
V2	tx_rx_only	spi_host_smoke	10.417m	50.459ms	47	50	94.00
V2	stress_all	spi_host_stress_all	3.767m	16.382ms	49	50	98.00
V2	spien	spi_host_spien	7.100m	33.293ms	50	50	100.00
V2	stall	spi_host_status_stall	9.467m	28.416ms	45	50	90.00
V2	Idlecsbactive	spi_host_idlecsbactive	44.000s	6.467ms	50	50	100.00
V2	alert_test	spi_host_alert_test	3.000s	36.760us	50	50	100.00
V2	intr_test	spi_host_intr_test	4.000s	130.701us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	9.000s	111.944us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	9.000s	111.944us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	3.000s	18.465us	5	5	100.00
		spi_host_csr_rw	3.000s	27.964us	20	20	100.00
		spi_host_csr_aliasing	4.000s	35.634us	5	5	100.00
		spi_host_same_csr_outstanding	4.000s	120.099us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	3.000s	18.465us	5	5	100.00
		spi_host_csr_rw	3.000s	27.964us	20	20	100.00
		spi_host_csr_aliasing	4.000s	35.634us	5	5	100.00
		spi_host_same_csr_outstanding	4.000s	120.099us	20	20	100.00
V2		TOTAL			683	690	98.99
V2S	tl_intg_err	spi_host_tl_intg_err	8.000s	151.492us	20	20	100.00
		spi_host_sec_cm	3.000s	59.546us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	8.000s	151.492us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	winbond	winbond			0	0	--
V3	stress_all_with_rand_reset	spi_host_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			820	830	98.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	15	15	12	80.00
V2S	2	2	2	100.00
V3	2	0	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.00	98.03	95.77	99.67	96.70	95.70	100.00	98.60	90.87

Failure Buckets

UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 8 failures:
- Test spi_host_status_stall has 3 failures.
  - 4.spi_host_status_stall.10580227614594123116007442197487128411867708204464020218917934061768385502987
    Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 66093067021 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x3ae273d4) == 0x0
  UVM_INFO @ 66093067021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 15.spi_host_status_stall.2188108203447825527874543920476452551134093687567200411931436298305692138856
    Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/15.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 129706226459 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xfc3a3554) == 0x0
  UVM_INFO @ 129706226459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test spi_host_smoke has 3 failures.
  - 12.spi_host_smoke.50499125692420877981298315395430035494908352305614358755443988243478346650826
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/12.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 97642668180 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xbee00114) == 0x0
  UVM_INFO @ 97642668180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 21.spi_host_smoke.51210656706071381740259835331388558449765003551130119820020376062362719179982
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/21.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 81191746132 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x382bd154) == 0x0
  UVM_INFO @ 81191746132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test spi_host_stress_all has 1 failures.
  - 23.spi_host_stress_all.107290450565182420177529806312532779255208509396379946749245584450151972147575
    Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/23.spi_host_stress_all/latest/run.log
```
  UVM_FATAL @ 29718931694 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x2bc12d54) == 0x0
  UVM_INFO @ 29718931694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_speed has 1 failures.
  - 47.spi_host_speed.52856347826156122772929555286559643961586857079903628132537695566461300693403
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/47.spi_host_speed/latest/run.log
```
  UVM_FATAL @ 72675571862 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x8ee1ea54) == 0x0
  UVM_INFO @ 72675571862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 2 failures:
- Test spi_host_status_stall has 2 failures.
  - 16.spi_host_status_stall.28690498665266671668803179134260315553483540209715238434429035560498838488022
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/16.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 17742633404 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xf198ff54) == 0x1
  UVM_INFO @ 17742633404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 35.spi_host_status_stall.81123885072315264255195499055857055348793258634304397885345607005375568028569
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/35.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 27850143292 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x20a5e094) == 0x1
  UVM_INFO @ 27850143292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SPI_HOST Simulation Results

Tuesday March 19 2024 19:02:40 UTC

GitHub Revision: f7fc348358

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 93166527750821992054916907919379261408154533955814283538537589225972237641118

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `f7fc348358`