SPI_HOST Simulation Results

Thursday March 21 2024 19:02:46 UTC

GitHub Revision: `e3ca274e77`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 110450978848188291656921294920309436568649534904994074551053469482156204817270

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	11.400m	53.872ms	47	50	94.00
V1	csr_hw_reset	spi_host_csr_hw_reset	5.000s	20.753us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	4.000s	16.868us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	9.000s	35.831us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	3.000s	51.352us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	7.000s	72.646us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	4.000s	16.868us	20	20	100.00
		spi_host_csr_aliasing	3.000s	51.352us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	4.000s	17.214us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	3.000s	22.245us	5	5	100.00
V1		TOTAL			112	115	97.39
V2	performance	spi_host_performance	4.000s	31.401us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	3.933m	26.265ms	50	50	100.00
		spi_host_error_cmd	4.000s	18.597us	50	50	100.00
		spi_host_event	22.533m	32.248ms	50	50	100.00
V2	clock_rate	spi_host_speed	5.200m	6.690ms	50	50	100.00
V2	speed	spi_host_speed	5.200m	6.690ms	50	50	100.00
V2	chip_select_timing	spi_host_speed	5.200m	6.690ms	50	50	100.00
V2	sw_reset	spi_host_sw_reset	3.900m	8.523ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	5.000s	389.864us	50	50	100.00
V2	cpol_cpha	spi_host_speed	5.200m	6.690ms	50	50	100.00
V2	full_cycle	spi_host_speed	5.200m	6.690ms	50	50	100.00
V2	duplex	spi_host_smoke	11.400m	53.872ms	47	50	94.00
V2	tx_rx_only	spi_host_smoke	11.400m	53.872ms	47	50	94.00
V2	stress_all	spi_host_stress_all	4.967m	15.973ms	49	50	98.00
V2	spien	spi_host_spien	7.250m	31.556ms	50	50	100.00
V2	stall	spi_host_status_stall	9.733m	13.852ms	46	50	92.00
V2	Idlecsbactive	spi_host_idlecsbactive	44.000s	6.836ms	50	50	100.00
V2	alert_test	spi_host_alert_test	4.000s	18.344us	50	50	100.00
V2	intr_test	spi_host_intr_test	4.000s	23.122us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	11.000s	93.504us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	11.000s	93.504us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	5.000s	20.753us	5	5	100.00
		spi_host_csr_rw	4.000s	16.868us	20	20	100.00
		spi_host_csr_aliasing	3.000s	51.352us	5	5	100.00
		spi_host_same_csr_outstanding	4.000s	21.501us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	5.000s	20.753us	5	5	100.00
		spi_host_csr_rw	4.000s	16.868us	20	20	100.00
		spi_host_csr_aliasing	3.000s	51.352us	5	5	100.00
		spi_host_same_csr_outstanding	4.000s	21.501us	20	20	100.00
V2		TOTAL			685	690	99.28
V2S	tl_intg_err	spi_host_tl_intg_err	5.000s	819.152us	20	20	100.00
		spi_host_sec_cm	5.000s	69.849us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	5.000s	819.152us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	winbond	winbond			0	0	--
V3	stress_all_with_rand_reset	spi_host_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			822	830	99.04

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	15	15	13	86.67
V2S	2	2	2	100.00
V3	2	0	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.83	97.85	95.41	99.45	96.64	95.70	100.00	98.60	90.87

Failure Buckets

UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 3 failures:
- Test spi_host_status_stall has 2 failures.
  - 4.spi_host_status_stall.86710770313866785613909904771014461734034717526468658813200434365321766467083
    Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 49437440846 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xde79d114) == 0x0
  UVM_INFO @ 49437440846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 44.spi_host_status_stall.94771489491116265357233833471366193394690671170886776228570904568991061960201
    Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/44.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 70120715214 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xfe26c9d4) == 0x0
  UVM_INFO @ 70120715214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_smoke has 1 failures.
  - 18.spi_host_smoke.106332858397935488873082698532247601217058221750983831932964397609276817429264
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/18.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 84455402706 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xaf160914) == 0x0
  UVM_INFO @ 84455402706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test spi_host_smoke has 1 failures.
  - 14.spi_host_smoke.115501013741498309164969895406940623204753169164423710874294558302478144199869
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/14.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 1 failures:
- Test spi_host_status_stall has 1 failures.
  - 25.spi_host_status_stall.18163429532111156665585881028231892392692715604513292561735028190359541353838
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/25.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 55908514689 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xf67806d4) == 0x1
  UVM_INFO @ 55908514689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test spi_host_smoke has 1 failures.
  - 29.spi_host_smoke.112257550149548386015667432822847710476708605642522904562467732582259527253966
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/29.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 1 failures:
- Test spi_host_status_stall has 1 failures.
  - 45.spi_host_status_stall.111393873357034780094805224801099759334360851261455915003220644032437008887295
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/45.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 27413727310 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xc690b294) == 0x1
  UVM_INFO @ 27413727310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 1 failures:
- Test spi_host_stress_all has 1 failures.
  - 46.spi_host_stress_all.39576321679947252942759846583747107120707731825181074809275837300723843722970
    Line 299, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/46.spi_host_stress_all/latest/run.log
```
  UVM_FATAL @ 11110469913 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x9c698a14) == 0x0
  UVM_INFO @ 11110469913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SPI_HOST Simulation Results

Thursday March 21 2024 19:02:46 UTC

GitHub Revision: e3ca274e77

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 110450978848188291656921294920309436568649534904994074551053469482156204817270

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `e3ca274e77`