SPI_HOST Simulation Results

Sunday March 24 2024 19:02:40 UTC

GitHub Revision: `70ad420931`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 56687816123908180356912499273064417112757374299033127319246303583078997854118

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	9.283m	45.811ms	46	50	92.00
V1	csr_hw_reset	spi_host_csr_hw_reset	7.000s	44.690us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	7.000s	19.550us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	931.357us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	4.000s	114.003us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	5.000s	28.921us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	7.000s	19.550us	20	20	100.00
		spi_host_csr_aliasing	4.000s	114.003us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	3.000s	60.333us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	2.000s	40.409us	5	5	100.00
V1		TOTAL			111	115	96.52
V2	performance	spi_host_performance	8.000s	52.956us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	3.350m	4.714ms	50	50	100.00
		spi_host_error_cmd	8.000s	16.774us	50	50	100.00
		spi_host_event	23.450m	141.414ms	50	50	100.00
V2	clock_rate	spi_host_speed	6.950m	77.225ms	50	50	100.00
V2	speed	spi_host_speed	6.950m	77.225ms	50	50	100.00
V2	chip_select_timing	spi_host_speed	6.950m	77.225ms	50	50	100.00
V2	sw_reset	spi_host_sw_reset	7.817m	17.692ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	13.000s	515.692us	50	50	100.00
V2	cpol_cpha	spi_host_speed	6.950m	77.225ms	50	50	100.00
V2	full_cycle	spi_host_speed	6.950m	77.225ms	50	50	100.00
V2	duplex	spi_host_smoke	9.283m	45.811ms	46	50	92.00
V2	tx_rx_only	spi_host_smoke	9.283m	45.811ms	46	50	92.00
V2	stress_all	spi_host_stress_all	3.767m	8.702ms	50	50	100.00
V2	spien	spi_host_spien	5.667m	59.403ms	49	50	98.00
V2	stall	spi_host_status_stall	9.450m	71.672ms	46	50	92.00
V2	Idlecsbactive	spi_host_idlecsbactive	45.000s	2.805ms	50	50	100.00
V2	alert_test	spi_host_alert_test	8.000s	15.643us	50	50	100.00
V2	intr_test	spi_host_intr_test	4.000s	20.068us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	6.000s	568.255us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	6.000s	568.255us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	7.000s	44.690us	5	5	100.00
		spi_host_csr_rw	7.000s	19.550us	20	20	100.00
		spi_host_csr_aliasing	4.000s	114.003us	5	5	100.00
		spi_host_same_csr_outstanding	8.000s	105.310us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	7.000s	44.690us	5	5	100.00
		spi_host_csr_rw	7.000s	19.550us	20	20	100.00
		spi_host_csr_aliasing	4.000s	114.003us	5	5	100.00
		spi_host_same_csr_outstanding	8.000s	105.310us	20	20	100.00
V2		TOTAL			685	690	99.28
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	141.655us	20	20	100.00
		spi_host_sec_cm	3.000s	224.300us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	141.655us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	winbond	winbond			0	0	--
V3	stress_all_with_rand_reset	spi_host_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			821	830	98.92

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	15	15	13	86.67
V2S	2	2	2	100.00
V3	2	0	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
96.87	96.67	93.00	98.48	96.64	95.70	100.00	98.60	90.46

Failure Buckets

UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 4 failures:
- Test spi_host_status_stall has 2 failures.
  - 20.spi_host_status_stall.29240107385985492631167498009843566854438780367933661272551743360095110057446
    Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/20.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 120576395556 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x78659f14) == 0x0
  UVM_INFO @ 120576395556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 27.spi_host_status_stall.102676963973522936246310892057321491472565635324930918097363028191757835513736
    Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/27.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 55384059860 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x8dd10294) == 0x0
  UVM_INFO @ 55384059860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_smoke has 2 failures.
  - 35.spi_host_smoke.63284971204408595698502428448357138232384598099377410115961745800242845639525
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/35.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 66013970586 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x64fe0214) == 0x0
  UVM_INFO @ 66013970586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 38.spi_host_smoke.28995153793784144682064046601825302360654778696353686651081481270921506023612
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/38.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 141258268982 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x7001414) == 0x0
  UVM_INFO @ 141258268982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 3 failures:
- Test spi_host_status_stall has 1 failures.
  - 14.spi_host_status_stall.75971157906879195777213435950184620184431295414879937372714658667591087553335
    Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/14.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 60483254661 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xeb8a6314) == 0x0
  UVM_INFO @ 60483254661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_smoke has 2 failures.
  - 20.spi_host_smoke.24565532134731563787666541485849382509194096146737825905205724515435941194172
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/20.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 150236677337 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xe581abd4) == 0x0
  UVM_INFO @ 150236677337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 43.spi_host_smoke.36620157355730953614518437753692178149390112299636044940260724932772174567383
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/43.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 130995466948 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x7b1f10d4) == 0x0
  UVM_INFO @ 130995466948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 1 failures:
- Test spi_host_status_stall has 1 failures.
  - 22.spi_host_status_stall.64486340125341658155464044456903573648240570811199126014589299424311755973410
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/22.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 15306847705 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xf5772fd4) == 0x1
  UVM_INFO @ 15306847705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 1 failures:
- Test spi_host_spien has 1 failures.
  - 27.spi_host_spien.85343215148423590669418109735901466839337644896301083847623650892422669991952
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/27.spi_host_spien/latest/run.log
```
  UVM_FATAL @ 10010609159 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xb49f994) == 0x0
  UVM_INFO @ 10010609159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SPI_HOST Simulation Results

Sunday March 24 2024 19:02:40 UTC

GitHub Revision: 70ad420931

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 56687816123908180356912499273064417112757374299033127319246303583078997854118

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `70ad420931`