b111fbcef3
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | spi_host_smoke | 10.433m | 26.249ms | 45 | 50 | 90.00 |
V1 | csr_hw_reset | spi_host_csr_hw_reset | 3.000s | 29.097us | 5 | 5 | 100.00 |
V1 | csr_rw | spi_host_csr_rw | 3.000s | 58.109us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | spi_host_csr_bit_bash | 6.000s | 886.885us | 5 | 5 | 100.00 |
V1 | csr_aliasing | spi_host_csr_aliasing | 2.000s | 25.156us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 3.000s | 131.180us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 3.000s | 58.109us | 20 | 20 | 100.00 |
spi_host_csr_aliasing | 2.000s | 25.156us | 5 | 5 | 100.00 | ||
V1 | mem_walk | spi_host_mem_walk | 2.000s | 17.136us | 5 | 5 | 100.00 |
V1 | mem_partial_access | spi_host_mem_partial_access | 3.000s | 28.306us | 5 | 5 | 100.00 |
V1 | TOTAL | 110 | 115 | 95.65 | |||
V2 | performance | spi_host_performance | 4.000s | 422.672us | 50 | 50 | 100.00 |
V2 | error_event_intr | spi_host_overflow_underflow | 2.533m | 20.271ms | 50 | 50 | 100.00 |
spi_host_error_cmd | 3.000s | 17.751us | 50 | 50 | 100.00 | ||
spi_host_event | 18.917m | 27.785ms | 50 | 50 | 100.00 | ||
V2 | clock_rate | spi_host_speed | 6.617m | 144.877ms | 49 | 50 | 98.00 |
V2 | speed | spi_host_speed | 6.617m | 144.877ms | 49 | 50 | 98.00 |
V2 | chip_select_timing | spi_host_speed | 6.617m | 144.877ms | 49 | 50 | 98.00 |
V2 | sw_reset | spi_host_sw_reset | 7.400m | 15.823ms | 50 | 50 | 100.00 |
V2 | passthrough_mode | spi_host_passthrough_mode | 4.000s | 277.587us | 50 | 50 | 100.00 |
V2 | cpol_cpha | spi_host_speed | 6.617m | 144.877ms | 49 | 50 | 98.00 |
V2 | full_cycle | spi_host_speed | 6.617m | 144.877ms | 49 | 50 | 98.00 |
V2 | duplex | spi_host_smoke | 10.433m | 26.249ms | 45 | 50 | 90.00 |
V2 | tx_rx_only | spi_host_smoke | 10.433m | 26.249ms | 45 | 50 | 90.00 |
V2 | stress_all | spi_host_stress_all | 3.767m | 9.480ms | 50 | 50 | 100.00 |
V2 | spien | spi_host_spien | 6.683m | 28.015ms | 50 | 50 | 100.00 |
V2 | stall | spi_host_status_stall | 9.733m | 13.208ms | 46 | 50 | 92.00 |
V2 | Idlecsbactive | spi_host_idlecsbactive | 47.000s | 17.116ms | 50 | 50 | 100.00 |
V2 | alert_test | spi_host_alert_test | 3.000s | 18.899us | 50 | 50 | 100.00 |
V2 | intr_test | spi_host_intr_test | 3.000s | 18.819us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | spi_host_tl_errors | 4.000s | 93.953us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | spi_host_tl_errors | 4.000s | 93.953us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 3.000s | 29.097us | 5 | 5 | 100.00 |
spi_host_csr_rw | 3.000s | 58.109us | 20 | 20 | 100.00 | ||
spi_host_csr_aliasing | 2.000s | 25.156us | 5 | 5 | 100.00 | ||
spi_host_same_csr_outstanding | 4.000s | 60.658us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | spi_host_csr_hw_reset | 3.000s | 29.097us | 5 | 5 | 100.00 |
spi_host_csr_rw | 3.000s | 58.109us | 20 | 20 | 100.00 | ||
spi_host_csr_aliasing | 2.000s | 25.156us | 5 | 5 | 100.00 | ||
spi_host_same_csr_outstanding | 4.000s | 60.658us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 685 | 690 | 99.28 | |||
V2S | tl_intg_err | spi_host_tl_intg_err | 4.000s | 72.673us | 20 | 20 | 100.00 |
spi_host_sec_cm | 3.000s | 302.216us | 5 | 5 | 100.00 | ||
V2S | sec_cm_bus_integrity | spi_host_tl_intg_err | 4.000s | 72.673us | 20 | 20 | 100.00 |
V2S | TOTAL | 25 | 25 | 100.00 | |||
V3 | winbond | winbond | 0 | 0 | -- | ||
V3 | stress_all_with_rand_reset | spi_host_stress_all_with_rand_reset | 0 | 0 | -- | ||
V3 | TOTAL | 0 | 0 | -- | |||
TOTAL | 820 | 830 | 98.80 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 8 | 8 | 7 | 87.50 |
V2 | 15 | 15 | 13 | 86.67 |
V2S | 2 | 2 | 2 | 100.00 |
V3 | 2 | 0 | 0 | 0.00 |
Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
---|---|---|---|---|---|---|---|---|
96.87 | 96.67 | 93.00 | 98.48 | 96.55 | 95.70 | 100.00 | 98.60 | 90.87 |
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == *
has 7 failures:
Test spi_host_smoke has 4 failures.
0.spi_host_smoke.48590403151952364542618454978667162957874651884260111352390774542676692705860
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_smoke/latest/run.log
UVM_FATAL @ 109929268581 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xd93d8194) == 0x0
UVM_INFO @ 109929268581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
27.spi_host_smoke.114926541041645057748446753954109060579789039742589319739480337284785298485420
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/27.spi_host_smoke/latest/run.log
UVM_FATAL @ 87055022276 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xc9d9d114) == 0x0
UVM_INFO @ 87055022276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Test spi_host_status_stall has 2 failures.
2.spi_host_status_stall.99561775164893081298816911244208683414302470838738232540008842589788713937153
Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_status_stall/latest/run.log
UVM_FATAL @ 132805964601 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x2cd257d4) == 0x0
UVM_INFO @ 132805964601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.spi_host_status_stall.22065799352538791472135349663776762117280073223308232124071289801661344016209
Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/20.spi_host_status_stall/latest/run.log
UVM_FATAL @ 23316333879 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x71d34d14) == 0x0
UVM_INFO @ 23316333879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_speed has 1 failures.
34.spi_host_speed.2918598798783702593583534330278583057097060684517564446353434012286051842762
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/34.spi_host_speed/latest/run.log
UVM_FATAL @ 144876505493 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xff01ba94) == 0x0
UVM_INFO @ 144876505493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == *
has 2 failures:
11.spi_host_status_stall.69285901875708372611508723419275922154839262375741123073289859813001807900735
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/11.spi_host_status_stall/latest/run.log
UVM_FATAL @ 21052224054 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x34f78e54) == 0x1
UVM_INFO @ 21052224054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
29.spi_host_status_stall.80147755227105671541189636314687753325660028445533049088688858538664030404217
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/29.spi_host_status_stall/latest/run.log
UVM_FATAL @ 17136382030 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x7050dd14) == 0x1
UVM_INFO @ 17136382030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
has 1 failures:
22.spi_host_smoke.821843519316063437571794304135205006403327789637195461249053345222996247494
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/22.spi_host_smoke/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---