SPI_HOST Simulation Results

Thursday March 28 2024 19:02:20 UTC

GitHub Revision: `4ee21f808f`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 29834210046083588839632889378999422318513504283488100050460647435812066910143

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	10.317m	54.258ms	50	50	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	7.000s	76.912us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	13.000s	16.149us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	15.000s	193.355us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	13.000s	58.662us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	8.000s	42.264us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	13.000s	16.149us	20	20	100.00
		spi_host_csr_aliasing	13.000s	58.662us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	12.000s	26.925us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	3.000s	37.797us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	performance	spi_host_performance	4.000s	104.460us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	3.500m	8.092ms	49	50	98.00
		spi_host_error_cmd	4.000s	126.228us	50	50	100.00
		spi_host_event	19.367m	114.569ms	50	50	100.00
V2	clock_rate	spi_host_speed	6.417m	8.746ms	50	50	100.00
V2	speed	spi_host_speed	6.417m	8.746ms	50	50	100.00
V2	chip_select_timing	spi_host_speed	6.417m	8.746ms	50	50	100.00
V2	sw_reset	spi_host_sw_reset	6.000m	11.635ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	4.000s	1.871ms	50	50	100.00
V2	cpol_cpha	spi_host_speed	6.417m	8.746ms	50	50	100.00
V2	full_cycle	spi_host_speed	6.417m	8.746ms	50	50	100.00
V2	duplex	spi_host_smoke	10.317m	54.258ms	50	50	100.00
V2	tx_rx_only	spi_host_smoke	10.317m	54.258ms	50	50	100.00
V2	stress_all	spi_host_stress_all	5.167m	11.473ms	48	50	96.00
V2	spien	spi_host_spien	5.450m	14.260ms	50	50	100.00
V2	stall	spi_host_status_stall	7.850m	23.111ms	48	50	96.00
V2	Idlecsbactive	spi_host_idlecsbactive	47.000s	1.669ms	50	50	100.00
V2	alert_test	spi_host_alert_test	3.000s	16.806us	50	50	100.00
V2	intr_test	spi_host_intr_test	13.000s	39.678us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	8.000s	91.564us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	8.000s	91.564us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	7.000s	76.912us	5	5	100.00
		spi_host_csr_rw	13.000s	16.149us	20	20	100.00
		spi_host_csr_aliasing	13.000s	58.662us	5	5	100.00
		spi_host_same_csr_outstanding	13.000s	47.567us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	7.000s	76.912us	5	5	100.00
		spi_host_csr_rw	13.000s	16.149us	20	20	100.00
		spi_host_csr_aliasing	13.000s	58.662us	5	5	100.00
		spi_host_same_csr_outstanding	13.000s	47.567us	20	20	100.00
V2		TOTAL			685	690	99.28
V2S	tl_intg_err	spi_host_tl_intg_err	15.000s	117.687us	20	20	100.00
		spi_host_sec_cm	8.000s	130.568us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	15.000s	117.687us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	winbond	winbond			0	0	--
V3	stress_all_with_rand_reset	spi_host_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			825	830	99.40

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	15	15	12	80.00
V2S	2	2	2	100.00
V3	2	0	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
96.87	96.67	93.00	98.48	96.64	95.70	100.00	98.60	90.46

Failure Buckets

UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 2 failures:
- Test spi_host_overflow_underflow has 1 failures.
  - 13.spi_host_overflow_underflow.48405413624756643905993968710053317079650382128544212945940749998138338252390
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/13.spi_host_overflow_underflow/latest/run.log
```
  UVM_FATAL @ 43559546218 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x16fcb294) == 0x0
  UVM_INFO @ 43559546218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_stress_all has 1 failures.
  - 21.spi_host_stress_all.27214899049657971250581314281505304848637945841577759848876476066353180712506
    Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/21.spi_host_stress_all/latest/run.log
```
  UVM_FATAL @ 10223044785 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x77c2ab54) == 0x0
  UVM_INFO @ 10223044785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 1 failures:
- Test spi_host_stress_all has 1 failures.
  - 32.spi_host_stress_all.29067960264033342532400226858573242004137477467061183256794259314783115796374
    Line 297, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/32.spi_host_stress_all/latest/run.log
```
  UVM_FATAL @ 11473468046 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xfe54ad14) == 0x0
  UVM_INFO @ 11473468046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 1 failures:
- Test spi_host_status_stall has 1 failures.
  - 34.spi_host_status_stall.34580462734723011478446654418185702124537484295237537537371270919697930767762
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/34.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 48037289394 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x719adf14) == 0x1
  UVM_INFO @ 48037289394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 1 failures:
- Test spi_host_status_stall has 1 failures.
  - 36.spi_host_status_stall.73307774726166132697209828892442945727958668090795812294799093292061494135291
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/36.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 17735180869 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xcc7bc754) == 0x1
  UVM_INFO @ 17735180869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SPI_HOST Simulation Results

Thursday March 28 2024 19:02:20 UTC

GitHub Revision: 4ee21f808f

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 29834210046083588839632889378999422318513504283488100050460647435812066910143

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `4ee21f808f`