SPI_HOST Simulation Results

Sunday March 31 2024 19:03:23 UTC

GitHub Revision: `919341eb22`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 80856351313811177568455658403012118288310064949310327557570531903004064389549

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	10.517m	52.092ms	48	50	96.00
V1	csr_hw_reset	spi_host_csr_hw_reset	3.000s	15.558us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	4.000s	16.717us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	6.000s	453.849us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	3.000s	42.824us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	9.000s	47.014us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	4.000s	16.717us	20	20	100.00
		spi_host_csr_aliasing	3.000s	42.824us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	3.000s	49.653us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	3.000s	34.658us	5	5	100.00
V1		TOTAL			113	115	98.26
V2	performance	spi_host_performance	3.000s	104.389us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	2.800m	4.116ms	50	50	100.00
		spi_host_error_cmd	3.000s	44.893us	50	50	100.00
		spi_host_event	21.733m	126.256ms	50	50	100.00
V2	clock_rate	spi_host_speed	4.967m	6.190ms	49	50	98.00
V2	speed	spi_host_speed	4.967m	6.190ms	49	50	98.00
V2	chip_select_timing	spi_host_speed	4.967m	6.190ms	49	50	98.00
V2	sw_reset	spi_host_sw_reset	3.400m	7.852ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	3.000s	237.502us	50	50	100.00
V2	cpol_cpha	spi_host_speed	4.967m	6.190ms	49	50	98.00
V2	full_cycle	spi_host_speed	4.967m	6.190ms	49	50	98.00
V2	duplex	spi_host_smoke	10.517m	52.092ms	48	50	96.00
V2	tx_rx_only	spi_host_smoke	10.517m	52.092ms	48	50	96.00
V2	stress_all	spi_host_stress_all	3.317m	3.703ms	50	50	100.00
V2	spien	spi_host_spien	7.133m	44.935ms	50	50	100.00
V2	stall	spi_host_status_stall	8.767m	170.503ms	46	50	92.00
V2	Idlecsbactive	spi_host_idlecsbactive	40.000s	6.281ms	49	50	98.00
V2	data_fifo_status	data_fifo_status			0	0	--
V2	alert_test	spi_host_alert_test	3.000s	17.523us	50	50	100.00
V2	intr_test	spi_host_intr_test	12.000s	29.533us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	5.000s	60.761us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	5.000s	60.761us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	3.000s	15.558us	5	5	100.00
		spi_host_csr_rw	4.000s	16.717us	20	20	100.00
		spi_host_csr_aliasing	3.000s	42.824us	5	5	100.00
		spi_host_same_csr_outstanding	4.000s	193.907us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	3.000s	15.558us	5	5	100.00
		spi_host_csr_rw	4.000s	16.717us	20	20	100.00
		spi_host_csr_aliasing	3.000s	42.824us	5	5	100.00
		spi_host_same_csr_outstanding	4.000s	193.907us	20	20	100.00
V2		TOTAL			684	690	99.13
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	165.661us	20	20	100.00
		spi_host_sec_cm	3.000s	65.261us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	165.661us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	winbond	winbond			0	0	--
V3	stress_all_with_rand_reset	spi_host_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			822	830	99.04

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	15	12	75.00
V2S	2	2	2	100.00
V3	2	0	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
96.87	96.67	93.00	98.48	96.64	95.70	100.00	98.60	90.46

Failure Buckets

UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 7 failures:
- Test spi_host_idlecsbactive has 1 failures.
  - 0.spi_host_idlecsbactive.24152642187297089051067613179515748059758608977976735815194824996584239163843
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_idlecsbactive/latest/run.log
```
  UVM_FATAL @ 10061739381 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xdeb7be14) == 0x0
  UVM_INFO @ 10061739381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_speed has 1 failures.
  - 18.spi_host_speed.103518590528843928094101791838752208067524748215105627895888210858179456668049
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/18.spi_host_speed/latest/run.log
```
  UVM_FATAL @ 97914486143 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x8c7c9294) == 0x0
  UVM_INFO @ 97914486143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_status_stall has 3 failures.
  - 26.spi_host_status_stall.25636588552668031106305394562834890158523800833348116512920180982270561823028
    Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/26.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 170503213191 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x303b90d4) == 0x0
  UVM_INFO @ 170503213191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 29.spi_host_status_stall.26218235129819312488357367821705222270955301543863789095651294426778705122693
    Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/29.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 15603292285 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x8f463d4) == 0x0
  UVM_INFO @ 15603292285 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test spi_host_smoke has 2 failures.
  - 32.spi_host_smoke.80700702613697496136248964259040845052264372479165925415862996845138551890710
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/32.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 173115734092 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xf28c3094) == 0x0
  UVM_INFO @ 173115734092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 33.spi_host_smoke.52456501734662204824441548130787985120127673229960290492448521149606406297444
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/33.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 93116428478 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x649f1154) == 0x0
  UVM_INFO @ 93116428478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 1 failures:
- Test spi_host_status_stall has 1 failures.
  - 25.spi_host_status_stall.113057021253349969955508644603505786192776749096364914062972996872673266852809
    Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/25.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 25898242863 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xe8d0e214) == 0x1
  UVM_INFO @ 25898242863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SPI_HOST Simulation Results

Sunday March 31 2024 19:03:23 UTC

GitHub Revision: 919341eb22

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 80856351313811177568455658403012118288310064949310327557570531903004064389549

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `919341eb22`