1fbe1ece8d| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_host_smoke | 9.867m | 21.056ms | 49 | 50 | 98.00 |
| V1 | csr_hw_reset | spi_host_csr_hw_reset | 2.000s | 41.036us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_host_csr_rw | 8.000s | 39.063us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_host_csr_bit_bash | 5.000s | 2.038ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_host_csr_aliasing | 13.000s | 137.226us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 12.000s | 92.370us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 8.000s | 39.063us | 20 | 20 | 100.00 |
| spi_host_csr_aliasing | 13.000s | 137.226us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_host_mem_walk | 2.000s | 14.706us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_host_mem_partial_access | 3.000s | 48.707us | 5 | 5 | 100.00 |
| V1 | TOTAL | 114 | 115 | 99.13 | |||
| V2 | performance | spi_host_performance | 14.000s | 32.704us | 50 | 50 | 100.00 |
| V2 | error_event_intr | spi_host_overflow_underflow | 2.483m | 11.474ms | 50 | 50 | 100.00 |
| spi_host_error_cmd | 3.000s | 20.354us | 50 | 50 | 100.00 | ||
| spi_host_event | 16.300m | 309.060ms | 50 | 50 | 100.00 | ||
| V2 | clock_rate | spi_host_speed | 5.217m | 33.660ms | 49 | 50 | 98.00 |
| V2 | speed | spi_host_speed | 5.217m | 33.660ms | 49 | 50 | 98.00 |
| V2 | chip_select_timing | spi_host_speed | 5.217m | 33.660ms | 49 | 50 | 98.00 |
| V2 | sw_reset | spi_host_sw_reset | 8.267m | 40.212ms | 50 | 50 | 100.00 |
| V2 | passthrough_mode | spi_host_passthrough_mode | 8.000s | 1.123ms | 50 | 50 | 100.00 |
| V2 | cpol_cpha | spi_host_speed | 5.217m | 33.660ms | 49 | 50 | 98.00 |
| V2 | full_cycle | spi_host_speed | 5.217m | 33.660ms | 49 | 50 | 98.00 |
| V2 | duplex | spi_host_smoke | 9.867m | 21.056ms | 49 | 50 | 98.00 |
| V2 | tx_rx_only | spi_host_smoke | 9.867m | 21.056ms | 49 | 50 | 98.00 |
| V2 | stress_all | spi_host_stress_all | 4.067m | 16.932ms | 50 | 50 | 100.00 |
| V2 | spien | spi_host_spien | 5.517m | 7.517ms | 50 | 50 | 100.00 |
| V2 | stall | spi_host_status_stall | 8.567m | 63.605ms | 47 | 50 | 94.00 |
| V2 | Idlecsbactive | spi_host_idlecsbactive | 41.000s | 3.281ms | 49 | 50 | 98.00 |
| V2 | data_fifo_status | data_fifo_status | 0 | 0 | -- | ||
| V2 | alert_test | spi_host_alert_test | 4.000s | 46.533us | 50 | 50 | 100.00 |
| V2 | intr_test | spi_host_intr_test | 8.000s | 26.826us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_host_tl_errors | 9.000s | 78.408us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_host_tl_errors | 9.000s | 78.408us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 2.000s | 41.036us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 8.000s | 39.063us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 13.000s | 137.226us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 8.000s | 28.238us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_host_csr_hw_reset | 2.000s | 41.036us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 8.000s | 39.063us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 13.000s | 137.226us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 8.000s | 28.238us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 685 | 690 | 99.28 | |||
| V2S | tl_intg_err | spi_host_tl_intg_err | 9.000s | 154.503us | 20 | 20 | 100.00 |
| spi_host_sec_cm | 3.000s | 123.345us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_host_tl_intg_err | 9.000s | 154.503us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | winbond | winbond | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | spi_host_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 824 | 830 | 99.28 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 16 | 15 | 12 | 75.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 2 | 0 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 96.89 | 96.67 | 93.00 | 98.48 | 96.73 | 95.70 | 100.00 | 98.60 | 90.87 |
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 4 failures:
Test spi_host_idlecsbactive has 1 failures.
0.spi_host_idlecsbactive.44578894148197477681378861800456906843019766015633108789178243229860714307353
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10041764406 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x2b16ba94) == 0x0
UVM_INFO @ 10041764406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_speed has 1 failures.
24.spi_host_speed.85996763122289934727079556337266275027675580041936977497373229581818117339957
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/24.spi_host_speed/latest/run.log
UVM_FATAL @ 105925179420 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x8be18cd4) == 0x0
UVM_INFO @ 105925179420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_smoke has 1 failures.
26.spi_host_smoke.47113233945336676187219201263105346035045665120978679067636101623130774643607
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/26.spi_host_smoke/latest/run.log
UVM_FATAL @ 71133174224 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x1f770f54) == 0x0
UVM_INFO @ 71133174224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_status_stall has 1 failures.
41.spi_host_status_stall.14083827359382303633324244815688739848715547255798740662615023730413892974762
Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/41.spi_host_status_stall/latest/run.log
UVM_FATAL @ 79621552421 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x1ee4ffd4) == 0x0
UVM_INFO @ 79621552421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 2 failures:
2.spi_host_status_stall.111972560923187175441743624386460993034836978638544031092783751967862134871383
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_status_stall/latest/run.log
UVM_FATAL @ 46686640407 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x302c2914) == 0x1
UVM_INFO @ 46686640407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
31.spi_host_status_stall.30570337450976116445911951497614514019388969329327248389426175898224895791400
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/31.spi_host_status_stall/latest/run.log
UVM_FATAL @ 48531834780 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xdb578654) == 0x1
UVM_INFO @ 48531834780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---